Simulation Results: dma

 
22/04/2026 19:39:07 DVSim: v1.32.0 sha: 062f5b3 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.46 %
  • code
  • 92.20 %
  • assert
  • 95.97 %
  • func
  • 65.20 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 4.000s 264.256us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 255.256us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 4.000s 309.188us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 54.652us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 42.680us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 8.000s 4998.799us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 5.000s 1195.066us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 1.000s 81.525us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 42.680us 1 1 100.00
dma_csr_aliasing 5.000s 1195.066us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 55.000s 4283.350us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 349.000s 84788.575us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 292.000s 46626.266us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 292.000s 46626.266us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 349.000s 84788.575us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 425.000s 57082.095us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 292.000s 46626.266us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 7.000s 892.999us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 203.000s 19454.728us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 57.048us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 2.000s 13.614us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 55.127us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 55.127us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 54.652us 1 1 100.00
dma_csr_rw 2.000s 42.680us 1 1 100.00
dma_csr_aliasing 5.000s 1195.066us 1 1 100.00
dma_same_csr_outstanding 3.000s 158.667us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 54.652us 1 1 100.00
dma_csr_rw 2.000s 42.680us 1 1 100.00
dma_csr_aliasing 5.000s 1195.066us 1 1 100.00
dma_same_csr_outstanding 3.000s 158.667us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 18.000s 813.855us 1 1 100.00
dma_generic_stress 425.000s 57082.095us 1 1 100.00
dma_handshake_stress 292.000s 46626.266us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 6.000s 2423.863us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 2.000s 500.747us 1 1 100.00
dma_sec_cm 1.000s 16.025us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 120.000s 26934.303us 1 1 100.00
dma_longer_transfer 6.000s 277.798us 1 1 100.00
dma_stress_all_with_rand_reset 11.000s 561.393us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 16380815687640516251737241105057942194458311301611711717355588082744162137991 117
UVM_INFO @ 561393154ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---