Simulation Results: edn/edn0

 
22/04/2026 19:39:07 DVSim: v1.32.0 sha: 062f5b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.64 %
  • code
  • 84.21 %
  • assert
  • 96.96 %
  • func
  • 81.75 %
  • line
  • 98.32 %
  • branch
  • 94.28 %
  • cond
  • 88.33 %
  • toggle
  • 86.87 %
  • FSM
  • 53.23 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.880s 25.798us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.910s 17.058us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.940s 45.700us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.100s 116.478us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.330s 34.980us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.340s 31.010us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.940s 45.700us 1 1 100.00
edn_csr_aliasing 1.330s 34.980us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.870s 132.580us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.870s 132.580us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.870s 132.580us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.110s 27.409us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.520s 55.570us 1 1 100.00
errs 1 1 100.00
edn_err 1.310s 24.769us 1 1 100.00
disable 1 2 50.00
edn_disable 0.940s 44.804us 1 1 100.00
edn_disable_auto_req_mode 2.470s 500.000us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 2.680s 696.553us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.850s 40.641us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.210s 16.408us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.450s 512.207us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.450s 512.207us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.910s 17.058us 1 1 100.00
edn_csr_rw 0.940s 45.700us 1 1 100.00
edn_csr_aliasing 1.330s 34.980us 1 1 100.00
edn_same_csr_outstanding 1.030s 18.603us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.910s 17.058us 1 1 100.00
edn_csr_rw 0.940s 45.700us 1 1 100.00
edn_csr_aliasing 1.330s 34.980us 1 1 100.00
edn_same_csr_outstanding 1.030s 18.603us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 7.200s 2253.801us 1 1 100.00
edn_tl_intg_err 1.350s 357.836us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.990s 43.303us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.520s 55.570us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.200s 2253.801us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.200s 2253.801us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.200s 2253.801us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.200s 2253.801us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.520s 55.570us 1 1 100.00
edn_sec_cm 7.200s 2253.801us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.520s 55.570us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.350s 357.836us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 19.950s 4618.473us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 108239426220666683206658408236331445311467744213882839907519215513131151888268 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---