Simulation Results: edn/edn1

 
22/04/2026 19:39:07 DVSim: v1.32.0 sha: 062f5b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.37 %
  • code
  • 79.07 %
  • assert
  • 97.14 %
  • func
  • 76.89 %
  • line
  • 96.66 %
  • branch
  • 88.53 %
  • cond
  • 82.85 %
  • toggle
  • 93.20 %
  • FSM
  • 34.09 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.020s 53.538us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.910s 26.174us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.840s 40.905us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.670s 541.499us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.330s 51.638us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.120s 51.189us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.840s 40.905us 1 1 100.00
edn_csr_aliasing 1.330s 51.638us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.200s 38.784us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.200s 38.784us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.200s 38.784us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.970s 21.411us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.040s 41.861us 1 1 100.00
errs 1 1 100.00
edn_err 0.960s 20.982us 1 1 100.00
disable 1 2 50.00
edn_disable 0.870s 34.955us 1 1 100.00
edn_disable_auto_req_mode 2.190s 500.000us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 3.840s 327.511us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.910s 18.683us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.820s 14.354us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.360s 42.180us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.360s 42.180us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.910s 26.174us 1 1 100.00
edn_csr_rw 0.840s 40.905us 1 1 100.00
edn_csr_aliasing 1.330s 51.638us 1 1 100.00
edn_same_csr_outstanding 1.180s 58.910us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.910s 26.174us 1 1 100.00
edn_csr_rw 0.840s 40.905us 1 1 100.00
edn_csr_aliasing 1.330s 51.638us 1 1 100.00
edn_same_csr_outstanding 1.180s 58.910us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.850s 776.087us 1 1 100.00
edn_tl_intg_err 2.580s 933.666us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.950s 83.115us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.040s 41.861us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.850s 776.087us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.850s 776.087us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.850s 776.087us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.850s 776.087us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.040s 41.861us 1 1 100.00
edn_sec_cm 2.850s 776.087us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.040s 41.861us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.580s 933.666us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 53.500s 3491.559us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 99418815194061991598228571323670298130919985255687960794234310293832939963652 331
UVM_INFO @ 3491558904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 82157557495833230905411137053780772142004813939191598296566617565376756510500 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---