Simulation Results: hmac

 
22/04/2026 19:39:07 DVSim: v1.32.0 sha: 062f5b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.54 %
  • code
  • 98.01 %
  • assert
  • 96.70 %
  • func
  • 43.91 %
  • line
  • 99.74 %
  • branch
  • 99.67 %
  • cond
  • 96.51 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 6.950s 12156.702us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.980s 36.669us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.860s 212.200us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 5.040s 532.948us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.110s 774.483us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 0.940s 51.704us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.860s 212.200us 1 1 100.00
hmac_csr_aliasing 6.110s 774.483us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 51.330s 1266.741us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 77.910s 3503.097us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 11.150s 315.246us 1 1 100.00
hmac_test_sha384_vectors 442.990s 25473.257us 1 1 100.00
hmac_test_sha512_vectors 453.690s 13848.999us 1 1 100.00
hmac_test_hmac256_vectors 10.270s 649.205us 1 1 100.00
hmac_test_hmac384_vectors 11.660s 628.279us 1 1 100.00
hmac_test_hmac512_vectors 9.180s 1009.056us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 1.910s 381.906us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 630.220s 17166.107us 1 1 100.00
error 1 1 100.00
hmac_error 5.080s 552.983us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 101.400s 38485.526us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 6.950s 12156.702us 1 1 100.00
hmac_long_msg 51.330s 1266.741us 1 1 100.00
hmac_back_pressure 77.910s 3503.097us 1 1 100.00
hmac_datapath_stress 630.220s 17166.107us 1 1 100.00
hmac_burst_wr 1.910s 381.906us 1 1 100.00
hmac_stress_all 157.230s 12208.086us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 6.950s 12156.702us 1 1 100.00
hmac_long_msg 51.330s 1266.741us 1 1 100.00
hmac_back_pressure 77.910s 3503.097us 1 1 100.00
hmac_datapath_stress 630.220s 17166.107us 1 1 100.00
hmac_wipe_secret 101.400s 38485.526us 1 1 100.00
hmac_test_sha256_vectors 11.150s 315.246us 1 1 100.00
hmac_test_sha384_vectors 442.990s 25473.257us 1 1 100.00
hmac_test_sha512_vectors 453.690s 13848.999us 1 1 100.00
hmac_test_hmac256_vectors 10.270s 649.205us 1 1 100.00
hmac_test_hmac384_vectors 11.660s 628.279us 1 1 100.00
hmac_test_hmac512_vectors 9.180s 1009.056us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 6.950s 12156.702us 1 1 100.00
hmac_long_msg 51.330s 1266.741us 1 1 100.00
hmac_back_pressure 77.910s 3503.097us 1 1 100.00
hmac_datapath_stress 630.220s 17166.107us 1 1 100.00
hmac_burst_wr 1.910s 381.906us 1 1 100.00
hmac_error 5.080s 552.983us 1 1 100.00
hmac_wipe_secret 101.400s 38485.526us 1 1 100.00
hmac_test_sha256_vectors 11.150s 315.246us 1 1 100.00
hmac_test_sha384_vectors 442.990s 25473.257us 1 1 100.00
hmac_test_sha512_vectors 453.690s 13848.999us 1 1 100.00
hmac_test_hmac256_vectors 10.270s 649.205us 1 1 100.00
hmac_test_hmac384_vectors 11.660s 628.279us 1 1 100.00
hmac_test_hmac512_vectors 9.180s 1009.056us 1 1 100.00
hmac_stress_all 157.230s 12208.086us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 157.230s 12208.086us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.700s 24.055us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.630s 19.294us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.530s 164.408us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.530s 164.408us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.980s 36.669us 1 1 100.00
hmac_csr_rw 0.860s 212.200us 1 1 100.00
hmac_csr_aliasing 6.110s 774.483us 1 1 100.00
hmac_same_csr_outstanding 1.950s 200.681us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.980s 36.669us 1 1 100.00
hmac_csr_rw 0.860s 212.200us 1 1 100.00
hmac_csr_aliasing 6.110s 774.483us 1 1 100.00
hmac_same_csr_outstanding 1.950s 200.681us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.100s 162.281us 1 1 100.00
hmac_tl_intg_err 2.850s 95.121us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.850s 95.121us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 6.950s 12156.702us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.500s 207.751us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 258.030s 17040.832us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.790s 17.516us 1 1 100.00