Simulation Results

Simulation Results: i2c

22/04/2026 19:39:07 DVSim: v1.32.0 sha: 062f5b3 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.77 %

code
81.52 %

assert
96.19 %

func
79.60 %

line
96.41 %

branch
92.41 %

cond
85.08 %

toggle
89.66 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		90.24%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	20.020s	1700.274us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	11.940s	4220.411us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.800s	55.074us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.870s	23.414us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	2.390s	693.978us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.210s	461.575us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.740s	25.968us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.870s	23.414us	1	1	100.00
	i2c_csr_aliasing	1.210s	461.575us	1	1	100.00

37/41 passed

90.24 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.980s	112.607us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	343.850s	30144.551us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	47.160s	6488.212us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.750s	33.440us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	75.090s	8897.693us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	90.260s	8363.146us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.600s	141.029us	1	1	100.00
	i2c_host_fifo_fmt_empty	15.410s	1085.899us	1	1	100.00
	i2c_host_fifo_reset_rx	5.230s	404.418us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	87.840s	4579.371us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	9.420s	897.989us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	2.140s	250.485us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.170s	557.458us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	63.930s	53803.314us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.490s	1504.314us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	10.010s	1439.246us	1	1	100.00
	i2c_target_intr_smoke	4.420s	1258.538us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.630s	378.190us	1	1	100.00
	i2c_target_fifo_reset_tx	2.120s	485.732us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	6.170s	37239.139us	1	1	100.00
	i2c_target_stress_rd	10.010s	1439.246us	1	1	100.00
	i2c_target_intr_stress_wr	58.220s	13072.351us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.130s	1187.899us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	18.610s	4344.130us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.870s	3652.134us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	1.470s	971.000us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.880s	294.934us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.030s	526.358us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	47.160s	6488.212us	1	1	100.00
	i2c_host_perf_precise	1.370s	305.075us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	9.420s	897.989us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	4.600s	424.055us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	2.010s	551.619us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.420s	1902.198us	1	1	100.00
	i2c_target_nack_txstretch	1.090s	503.241us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	4.200s	303.552us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.680s	2013.570us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.760s	28.940us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.010s	19.125us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.960s	251.661us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.960s	251.661us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.800s	55.074us	1	1	100.00
	i2c_csr_rw	0.870s	23.414us	1	1	100.00
	i2c_csr_aliasing	1.210s	461.575us	1	1	100.00
	i2c_same_csr_outstanding	1.330s	166.112us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.800s	55.074us	1	1	100.00
	i2c_csr_rw	0.870s	23.414us	1	1	100.00
	i2c_csr_aliasing	1.210s	461.575us	1	1	100.00
	i2c_same_csr_outstanding	1.330s	166.112us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.440s	411.393us	1	1	100.00
	i2c_sec_cm	0.990s	128.100us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.440s	411.393us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	11.890s	578.765us	1
target_error_intr				1
	i2c_target_unexp_stop	1.280s	363.271us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	26.450s	1891.129us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
	i2c_host_error_intr	57940206097786862930170357201571132768017554081041102693482110868073362672726	88	UVM_INFO @ 112607025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	104276253961494026025610980874169591876862076671686665513080492528648920104340	127	UVM_INFO @ 30144551497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	70216209466188304732366822305613882454075112138437259674383051100124753116753	115	UVM_INFO @ 1891129090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
	i2c_target_glitch	40610302870986949587456504263742103279781931086690227226739224081872023636697	84	UVM_INFO @ 557458198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [] vs [*])
	i2c_target_unexp_stop	108177061501432998227612524800744329409693167487395708822811858650308692853372	78	UVM_INFO @ 363271205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	i2c_host_stress_all_with_rand_reset	23984285687698892410290199745579139340975019196745646747245589176565657521952	88	UVM_INFO @ 578764996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:
	i2c_host_mode_toggle	77227132285930869410516116465926524991527595520233697102833535100807730294025	85	---------------------------------------------------- Name Type Size Value ---------------------------------------------------- mon_dut_item i2c_item - @35101