Simulation Results: kmac/unmasked

 
22/04/2026 19:39:07 DVSim: v1.32.0 sha: 062f5b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.91 %
  • code
  • 89.07 %
  • assert
  • 97.75 %
  • func
  • 91.92 %
  • line
  • 97.23 %
  • branch
  • 95.20 %
  • cond
  • 94.23 %
  • toggle
  • 100.00 %
  • FSM
  • 58.68 %
Validation stages
V1
100.00%
V2
96.55%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 37.090s 21959.366us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.970s 38.722us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.310s 89.366us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 19.200s 5987.422us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 7.510s 1910.905us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.860s 147.226us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.310s 89.366us 1 1 100.00
kmac_csr_aliasing 7.510s 1910.905us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.840s 14.686us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.160s 35.112us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 1571.850s 85093.883us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 525.790s 83200.698us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 25.130s 635.267us 1 1 100.00
kmac_test_vectors_sha3_256 27.880s 1833.230us 1 1 100.00
kmac_test_vectors_sha3_384 1020.010s 238604.676us 1 1 100.00
kmac_test_vectors_sha3_512 721.350s 31681.725us 1 1 100.00
kmac_test_vectors_shake_128 1398.420s 20906.867us 1 1 100.00
kmac_test_vectors_shake_256 84.240s 12405.946us 1 1 100.00
kmac_test_vectors_kmac 2.250s 34.001us 1 1 100.00
kmac_test_vectors_kmac_xof 2.040s 269.943us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 50.780s 3289.019us 1 1 100.00
app 1 1 100.00
kmac_app 217.900s 19082.245us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 228.680s 16952.856us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 66.110s 38794.226us 1 1 100.00
error 1 1 100.00
kmac_error 79.820s 2986.877us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 3.350s 601.139us 1 1 100.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 29.320s 10282.202us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 14.770s 16164.125us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 31.510s 1492.968us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 14.750s 9240.708us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.560s 53.773us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 406.400s 7764.123us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.880s 25.971us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.860s 59.589us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.710s 41.911us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.710s 41.911us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.970s 38.722us 1 1 100.00
kmac_csr_rw 1.310s 89.366us 1 1 100.00
kmac_csr_aliasing 7.510s 1910.905us 1 1 100.00
kmac_same_csr_outstanding 1.350s 83.359us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.970s 38.722us 1 1 100.00
kmac_csr_rw 1.310s 89.366us 1 1 100.00
kmac_csr_aliasing 7.510s 1910.905us 1 1 100.00
kmac_same_csr_outstanding 1.350s 83.359us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 2.240s 205.803us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 2.240s 205.803us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 2.240s 205.803us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 2.240s 205.803us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.570s 58.406us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 20.050s 3074.612us 1 1 100.00
kmac_tl_intg_err 2.460s 194.041us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.460s 194.041us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.560s 53.773us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 37.090s 21959.366us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 50.780s 3289.019us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 2.240s 205.803us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 20.050s 3074.612us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 20.050s 3074.612us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 20.050s 3074.612us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 37.090s 21959.366us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.560s 53.773us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 20.050s 3074.612us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 132.680s 7693.887us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 37.090s 21959.366us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
kmac_stress_all_with_rand_reset 29.960s 5461.300us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13)
kmac_sideload_invalid 42308357102915866555318198755291147312724100340492899919536142944292451691321 91
UVM_INFO @ 10282202445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---