Simulation Results: lc_ctrl/volatile_unlock_disabled

 
22/04/2026 19:39:07 DVSim: v1.32.0 sha: 062f5b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.90 %
  • code
  • 84.43 %
  • assert
  • 95.99 %
  • func
  • 92.27 %
  • line
  • 97.69 %
  • branch
  • 95.70 %
  • cond
  • 79.67 %
  • toggle
  • 89.08 %
  • FSM
  • 60.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.500s 99.905us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.410s 29.438us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.220s 191.190us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.900s 95.272us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.640s 118.219us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.800s 36.107us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.220s 191.190us 1 1 100.00
lc_ctrl_csr_aliasing 1.640s 118.219us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.020s 437.352us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.970s 1479.411us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.960s 13.942us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.360s 85.159us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.900s 202.319us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.240s 375.913us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.900s 202.319us 1 1 100.00
lc_ctrl_prog_failure 2.360s 85.159us 1 1 100.00
lc_ctrl_errors 6.240s 375.913us 1 1 100.00
lc_ctrl_security_escalation 4.790s 1505.183us 1 1 100.00
lc_ctrl_jtag_state_failure 23.710s 29368.991us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.980s 912.658us 1 1 100.00
lc_ctrl_jtag_errors 45.470s 10984.864us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 1.540s 139.518us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.440s 2621.042us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.980s 912.658us 1 1 100.00
lc_ctrl_jtag_errors 45.470s 10984.864us 1 1 100.00
lc_ctrl_jtag_access 2.270s 192.300us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.510s 1885.506us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.440s 164.288us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.520s 196.984us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 12.090s 2731.718us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.810s 749.398us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.460s 27.898us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.100s 1730.537us 1 1 100.00
lc_ctrl_jtag_alert_test 1.640s 33.127us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.430s 663.338us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.770s 43.727us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 81.580s 8633.405us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.230s 22.761us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.800s 294.294us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.800s 294.294us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.410s 29.438us 1 1 100.00
lc_ctrl_csr_rw 1.220s 191.190us 1 1 100.00
lc_ctrl_csr_aliasing 1.640s 118.219us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.960s 132.360us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.410s 29.438us 1 1 100.00
lc_ctrl_csr_rw 1.220s 191.190us 1 1 100.00
lc_ctrl_csr_aliasing 1.640s 118.219us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.960s 132.360us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.160s 248.821us 1 1 100.00
lc_ctrl_tl_intg_err 1.320s 84.236us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.320s 84.236us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.970s 1479.411us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.900s 202.319us 1 1 100.00
lc_ctrl_sec_cm 5.160s 248.821us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.900s 202.319us 1 1 100.00
lc_ctrl_sec_cm 5.160s 248.821us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.900s 202.319us 1 1 100.00
lc_ctrl_sec_cm 5.160s 248.821us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.900s 202.319us 1 1 100.00
lc_ctrl_sec_cm 5.160s 248.821us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.900s 202.319us 1 1 100.00
lc_ctrl_sec_cm 5.160s 248.821us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.900s 202.319us 1 1 100.00
lc_ctrl_sec_cm 5.160s 248.821us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.900s 202.319us 1 1 100.00
lc_ctrl_sec_cm 5.160s 248.821us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.900s 202.319us 1 1 100.00
lc_ctrl_sec_cm 5.160s 248.821us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.790s 1505.183us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.020s 437.352us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.440s 2621.042us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.290s 1953.223us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.290s 1953.223us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.770s 518.104us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.190s 1028.349us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.190s 1028.349us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 12.290s 1546.563us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 58825199252838787978615033038551685466589951897991281990154942659612537270220 3241
UVM_INFO @ 1546562642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---