Simulation Results: lc_ctrl/volatile_unlock_enabled

 
22/04/2026 19:39:07 DVSim: v1.32.0 sha: 062f5b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.80 %
  • code
  • 85.88 %
  • assert
  • 95.99 %
  • func
  • 93.53 %
  • line
  • 97.55 %
  • branch
  • 96.01 %
  • cond
  • 79.15 %
  • toggle
  • 89.41 %
  • FSM
  • 67.27 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.250s 65.912us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.030s 59.968us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.830s 57.563us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.390s 261.795us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.480s 58.843us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.090s 46.188us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.830s 57.563us 1 1 100.00
lc_ctrl_csr_aliasing 1.480s 58.843us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.080s 227.216us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.650s 483.435us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.190s 12.783us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.860s 327.431us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.660s 222.036us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 10.340s 1547.879us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.660s 222.036us 1 1 100.00
lc_ctrl_prog_failure 2.860s 327.431us 1 1 100.00
lc_ctrl_errors 10.340s 1547.879us 1 1 100.00
lc_ctrl_security_escalation 5.520s 201.140us 1 1 100.00
lc_ctrl_jtag_state_failure 21.500s 5693.375us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.310s 1637.399us 1 1 100.00
lc_ctrl_jtag_errors 15.290s 1635.394us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.150s 141.533us 1 1 100.00
lc_ctrl_jtag_state_post_trans 14.630s 1915.304us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.310s 1637.399us 1 1 100.00
lc_ctrl_jtag_errors 15.290s 1635.394us 1 1 100.00
lc_ctrl_jtag_access 4.640s 284.220us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.300s 1652.108us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.740s 230.769us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.590s 248.482us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.010s 1529.106us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.930s 2197.244us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.510s 85.011us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.720s 347.254us 1 1 100.00
lc_ctrl_jtag_alert_test 1.390s 219.280us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.250s 363.173us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.070s 14.777us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 358.440s 18773.883us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.840s 99.798us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 108.127us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 108.127us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.030s 59.968us 1 1 100.00
lc_ctrl_csr_rw 0.830s 57.563us 1 1 100.00
lc_ctrl_csr_aliasing 1.480s 58.843us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.020s 27.583us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.030s 59.968us 1 1 100.00
lc_ctrl_csr_rw 0.830s 57.563us 1 1 100.00
lc_ctrl_csr_aliasing 1.480s 58.843us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.020s 27.583us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.440s 499.397us 1 1 100.00
lc_ctrl_tl_intg_err 1.640s 64.944us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.640s 64.944us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.650s 483.435us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.660s 222.036us 1 1 100.00
lc_ctrl_sec_cm 7.440s 499.397us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.660s 222.036us 1 1 100.00
lc_ctrl_sec_cm 7.440s 499.397us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.660s 222.036us 1 1 100.00
lc_ctrl_sec_cm 7.440s 499.397us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.660s 222.036us 1 1 100.00
lc_ctrl_sec_cm 7.440s 499.397us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.660s 222.036us 1 1 100.00
lc_ctrl_sec_cm 7.440s 499.397us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.660s 222.036us 1 1 100.00
lc_ctrl_sec_cm 7.440s 499.397us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.660s 222.036us 1 1 100.00
lc_ctrl_sec_cm 7.440s 499.397us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.660s 222.036us 1 1 100.00
lc_ctrl_sec_cm 7.440s 499.397us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.520s 201.140us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.080s 227.216us 1 1 100.00
lc_ctrl_jtag_state_post_trans 14.630s 1915.304us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.970s 2269.532us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.970s 2269.532us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 9.340s 793.700us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.690s 694.080us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.690s 694.080us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 121.880s 14607.409us 1 1 100.00