Simulation Results: mbx

 
22/04/2026 19:39:07 DVSim: v1.32.0 sha: 062f5b3 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.17 %
  • code
  • 91.68 %
  • assert
  • 96.76 %
  • func
  • 76.07 %
  • block
  • 97.01 %
  • line
  • 96.84 %
  • branch
  • 92.25 %
  • toggle
  • 85.96 %
Validation stages
V1
83.33%
V2
90.91%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 57.000s 31838.939us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 36.162us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 24.228us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 4.000s 415.616us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 32.671us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 1.000s 13.048us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 24.228us 1 1 100.00
mbx_csr_aliasing 2.000s 32.671us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 1 1 100.00
mbx_stress 47.000s 19713.096us 1 1 100.00
mbx_max_activity 1 1 100.00
mbx_stress_zero_delays 12.000s 2189.542us 1 1 100.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 25.000s 19612.230us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 18.000s 544.929us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 2.000s 20.050us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 16.295us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 10.692us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 10.692us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 36.162us 1 1 100.00
mbx_csr_rw 1.000s 24.228us 1 1 100.00
mbx_csr_aliasing 2.000s 32.671us 1 1 100.00
mbx_same_csr_outstanding 2.000s 47.592us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 36.162us 1 1 100.00
mbx_csr_rw 1.000s 24.228us 1 1 100.00
mbx_csr_aliasing 2.000s 32.671us 1 1 100.00
mbx_same_csr_outstanding 2.000s 47.592us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 750.796us 1 1 100.00
mbx_sec_cm 1.000s 53.380us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *).
mbx_tl_errors 75939651790475157889943476009199673758952898841595401350849604112433657979536 85
TL item was: req: (cip_tl_seq_item@15844) { a_addr: 'h26f30054 a_data: 'h44c618f6 a_mask: 'he a_size: 'h2 a_param: 'h0 a_source: 'h93 a_opcode: 'h1 a_user: 'h25c73 d_param: 'h0 d_source: 'h93 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 10692045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 112770218277739052792926269341405041513127995779646072222824927939436624326229 86
TL item was: req: (cip_tl_seq_item@15864) { a_addr: 'ha597d590 a_data: 'ha71a9ed0 a_mask: 'h0 a_size: 'h2 a_param: 'h0 a_source: 'hb5 a_opcode: 'h1 a_user: 'h265f0 d_param: 'h0 d_source: 'hb5 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 13048085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---