Simulation Results: otbn

 
22/04/2026 19:39:07 DVSim: v1.32.0 sha: 062f5b3 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.05 %
  • code
  • 95.13 %
  • assert
  • 89.57 %
  • func
  • 97.46 %
  • block
  • 99.35 %
  • line
  • 99.55 %
  • branch
  • 91.83 %
  • toggle
  • 91.71 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
92.86%
V2S
88.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 9.000s 76.014us 1 1 100.00
single_binary 1 1 100.00
otbn_single 11.000s 78.650us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 3.000s 17.454us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 3.000s 173.619us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 5.000s 68.209us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 3.000s 54.757us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 5.000s 93.808us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 3.000s 173.619us 1 1 100.00
otbn_csr_aliasing 3.000s 54.757us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 56.000s 9970.540us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 55.000s 1274.359us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 32.000s 565.620us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 47.000s 335.145us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 48.000s 658.972us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 21.000s 118.726us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 8.000s 20.301us 1 1 100.00
zero_state_err_urnd 0 1 0.00
otbn_zero_state_err_urnd 4.000s 11.271us 0 1 0.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 10.000s 53.732us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 4.000s 41.974us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 34.830us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 6.000s 184.892us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 6.000s 184.892us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 3.000s 17.454us 1 1 100.00
otbn_csr_rw 3.000s 173.619us 1 1 100.00
otbn_csr_aliasing 3.000s 54.757us 1 1 100.00
otbn_same_csr_outstanding 5.000s 40.799us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 3.000s 17.454us 1 1 100.00
otbn_csr_rw 3.000s 173.619us 1 1 100.00
otbn_csr_aliasing 3.000s 54.757us 1 1 100.00
otbn_same_csr_outstanding 5.000s 40.799us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 7.000s 61.043us 1 1 100.00
otbn_dmem_err 6.000s 20.902us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 8.000s 20.188us 1 1 100.00
otbn_controller_ispr_rdata_err 8.000s 51.674us 1 1 100.00
otbn_mac_bignum_acc_err 9.000s 70.736us 1 1 100.00
otbn_urnd_err 6.000s 54.884us 0 1 0.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 5.000s 31.032us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 6.000s 36.944us 1 1 100.00
otbn_non_sec_partial_wipe 0 1 0.00
otbn_partial_wipe 4.000s 11.489us 0 1 0.00
tl_intg_err 2 2 100.00
otbn_sec_cm 353.000s 2301.689us 1 1 100.00
otbn_tl_intg_err 16.000s 102.295us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 38.000s 451.128us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 353.000s 2301.689us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 353.000s 2301.689us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 9.000s 76.014us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 6.000s 20.902us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 7.000s 61.043us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 16.000s 102.295us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 8.000s 20.301us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 7.000s 61.043us 1 1 100.00
otbn_dmem_err 6.000s 20.902us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 11.271us 0 1 0.00
otbn_illegal_mem_acc 5.000s 31.032us 1 1 100.00
otbn_sec_cm 353.000s 2301.689us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 353.000s 2301.689us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 11.000s 78.650us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 7.000s 61.043us 1 1 100.00
otbn_dmem_err 6.000s 20.902us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 11.271us 0 1 0.00
otbn_illegal_mem_acc 5.000s 31.032us 1 1 100.00
otbn_sec_cm 353.000s 2301.689us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 353.000s 2301.689us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 8.000s 20.301us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 7.000s 61.043us 1 1 100.00
otbn_dmem_err 6.000s 20.902us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 11.271us 0 1 0.00
otbn_illegal_mem_acc 5.000s 31.032us 1 1 100.00
otbn_sec_cm 353.000s 2301.689us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 353.000s 2301.689us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 11.000s 78.650us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 5.000s 13.621us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 20.132us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 52.000s 222.789us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 52.000s 222.789us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 5.000s 50.921us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 353.000s 2301.689us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 353.000s 2301.689us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 9.000s 311.922us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 353.000s 2301.689us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 353.000s 2301.689us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 6.000s 13.943us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 6.000s 13.943us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 9.555us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 11.000s 78.650us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 11.000s 78.650us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 11.000s 78.650us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 48.000s 658.972us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 11.000s 78.650us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 11.000s 78.650us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 6.000s 18.705us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 11.000s 78.650us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 353.000s 2301.689us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 319.000s 1670.338us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 6.000s 17.799us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 77929378106210865604254967733075534567368793325578716454747249449117644475208 500
UVM_INFO @ 1670337631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
otbn_zero_state_err_urnd 43383728202682976704466314104718227767514123929783202468714644925961347210838 106
UVM_INFO @ 11270964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.edn_urnd_ack cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
otbn_urnd_err 9509238856549414201446959482921631143520741626921920362610208291827729379695 108
UVM_INFO @ 54883973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status
otbn_partial_wipe 63499451257789932794956250529757458773512027401039043959115845524798636847017 114
UVM_INFO @ 11489143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---