Simulation Results: otp_ctrl

 
22/04/2026 19:39:07 DVSim: v1.32.0 sha: 062f5b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 71.03 %
  • code
  • 70.00 %
  • assert
  • 93.08 %
  • func
  • 50.02 %
  • line
  • 87.11 %
  • branch
  • 83.43 %
  • cond
  • 85.47 %
  • toggle
  • 60.87 %
  • FSM
  • 33.12 %
Validation stages
V1
77.78%
V2
70.00%
V2S
66.67%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.990s 93.214us 1 1 100.00
smoke 0 1 0.00
otp_ctrl_smoke 3.320s 67.235us 0 1 0.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 3.450s 167.644us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.780s 175.818us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 3.170s 85.639us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 5.470s 184.484us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.860s 280.214us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.780s 175.818us 1 1 100.00
otp_ctrl_csr_aliasing 5.470s 184.484us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 2.080s 153.729us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.510s 142.637us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 106.100s 11336.613us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.040s 227.476us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 2.410s 811.340us 0 1 0.00
otp_ctrl_check_fail 3.360s 393.713us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 3.840s 156.711us 1 1 100.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 2.570s 134.401us 0 1 0.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 13.150s 1425.663us 1 1 100.00
lc_interactions 1 2 50.00
otp_ctrl_parallel_lc_req 5.740s 648.873us 0 1 0.00
otp_ctrl_parallel_lc_esc 16.530s 6555.047us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 25.500s 8231.710us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 19.140s 3515.515us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 5.570s 250.456us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 9.890s 374.296us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.860s 170.981us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 3.400s 234.331us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.630s 108.161us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.630s 108.161us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.450s 167.644us 1 1 100.00
otp_ctrl_csr_rw 1.780s 175.818us 1 1 100.00
otp_ctrl_csr_aliasing 5.470s 184.484us 1 1 100.00
otp_ctrl_same_csr_outstanding 6.430s 2934.388us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.450s 167.644us 1 1 100.00
otp_ctrl_csr_rw 1.780s 175.818us 1 1 100.00
otp_ctrl_csr_aliasing 5.470s 184.484us 1 1 100.00
otp_ctrl_same_csr_outstanding 6.430s 2934.388us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 276.170s 63414.708us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 276.170s 63414.708us 1 1 100.00
otp_ctrl_tl_intg_err 11.530s 795.343us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 276.170s 63414.708us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 276.170s 63414.708us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 11.530s 795.343us 1 1 100.00
sec_cm_secret_mem_scramble 0 1 0.00
otp_ctrl_smoke 3.320s 67.235us 0 1 0.00
sec_cm_part_mem_digest 0 1 0.00
otp_ctrl_smoke 3.320s 67.235us 0 1 0.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 276.170s 63414.708us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 276.170s 63414.708us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 276.170s 63414.708us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 276.170s 63414.708us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 276.170s 63414.708us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 276.170s 63414.708us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 276.170s 63414.708us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 276.170s 63414.708us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 276.170s 63414.708us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 276.170s 63414.708us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 276.170s 63414.708us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 276.170s 63414.708us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 276.170s 63414.708us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 276.170s 63414.708us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 276.170s 63414.708us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 16.530s 6555.047us 1 1 100.00
otp_ctrl_sec_cm 276.170s 63414.708us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 16.530s 6555.047us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 16.530s 6555.047us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 16.530s 6555.047us 1 1 100.00
otp_ctrl_macro_errs 19.140s 3515.515us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 16.530s 6555.047us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 16.530s 6555.047us 1 1 100.00
otp_ctrl_sec_cm 276.170s 63414.708us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 16.530s 6555.047us 1 1 100.00
otp_ctrl_sec_cm 276.170s 63414.708us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 16.530s 6555.047us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 16.530s 6555.047us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 16.530s 6555.047us 1 1 100.00
otp_ctrl_macro_errs 19.140s 3515.515us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 16.530s 6555.047us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 16.530s 6555.047us 1 1 100.00
otp_ctrl_sec_cm 276.170s 63414.708us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.040s 227.476us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 3.360s 393.713us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 2.570s 134.401us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 2.570s 134.401us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 2.570s 134.401us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 2.570s 134.401us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 2.570s 134.401us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
otp_ctrl_smoke 3.320s 67.235us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 2.570s 134.401us 0 1 0.00
sec_cm_test_bus_lc_gated 0 1 0.00
otp_ctrl_smoke 3.320s 67.235us 0 1 0.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 276.170s 63414.708us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 3.840s 156.711us 1 1 100.00
sec_cm_check_trigger_config_regwen 0 1 0.00
otp_ctrl_smoke 3.320s 67.235us 0 1 0.00
sec_cm_check_config_regwen 0 1 0.00
otp_ctrl_smoke 3.320s 67.235us 0 1 0.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 19.140s 3515.515us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 109.410s 46264.461us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 3.820s 118.402us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: *
otp_ctrl_smoke 11289678351081415312461656690326534246781738456565459977568056258997433096714 3090
UVM_INFO @ 67235243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch
otp_ctrl_partition_walk 7440853679433425680720896731831809547222599918885604455609027663230356441940 120727
UVM_INFO @ 11336613069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch
otp_ctrl_low_freq_read 12079307313953390619005019240980204429904147871019347412395340924768952139898 89
UVM_INFO @ 46264460838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_*
otp_ctrl_background_chks 26191732225668969232818922659367128510368822326662224212763782460474934675509 502
UVM_INFO @ 811339751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 5956857073209049171296541624674309389120177687892740760807100545648142485154 684
UVM_INFO @ 134400551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 79949331398093840925226377125466063929320620873811449994710800122479754912876 586
UVM_INFO @ 118401686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:671) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr
otp_ctrl_parallel_lc_req 99836773812694771154642655561956763459534018371437632816040395109918330713144 5427
UVM_INFO @ 648873493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 32928087279608474915095992156805448768682429242616066477134005539843873004694 14111
UVM_INFO @ 374296181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:958) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask *
otp_ctrl_check_fail 91827185668857063721312069689257846156967632027307655876065745592648502342834 2700
UVM_INFO @ 393712510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_csr_mem_rw_with_rand_reset 66377327456168552814433301906701816644721126108254180745160678214053073940484 97
UVM_INFO @ 280213543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---