Simulation Results: rom_ctrl/32kb

 
22/04/2026 19:39:07 DVSim: v1.32.0 sha: 062f5b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.02 %
  • code
  • 99.65 %
  • assert
  • 96.80 %
  • func
  • 97.61 %
  • line
  • 99.59 %
  • branch
  • 100.00 %
  • cond
  • 98.66 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.410s 1502.370us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.370s 333.057us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.980s 293.540us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.620s 209.170us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.960s 286.828us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.020s 1399.499us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.980s 293.540us 1 1 100.00
rom_ctrl_csr_aliasing 3.960s 286.828us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.560s 207.877us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.960s 386.079us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.700s 320.114us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 15.420s 612.807us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.240s 1039.187us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.440s 126.935us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.470s 171.928us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.470s 171.928us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.370s 333.057us 1 1 100.00
rom_ctrl_csr_rw 3.980s 293.540us 1 1 100.00
rom_ctrl_csr_aliasing 3.960s 286.828us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.390s 564.696us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.370s 333.057us 1 1 100.00
rom_ctrl_csr_rw 3.980s 293.540us 1 1 100.00
rom_ctrl_csr_aliasing 3.960s 286.828us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.390s 564.696us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 74.190s 2599.967us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 21.280s 5199.953us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 99.530s 2704.454us 1 1 100.00
rom_ctrl_tl_intg_err 43.410s 2673.848us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 99.530s 2704.454us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 99.530s 2704.454us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 74.190s 2599.967us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 74.190s 2599.967us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 74.190s 2599.967us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 74.190s 2599.967us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 74.190s 2599.967us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 99.530s 2704.454us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 99.530s 2704.454us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.410s 1502.370us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.410s 1502.370us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.410s 1502.370us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 43.410s 2673.848us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 74.190s 2599.967us 1 1 100.00
rom_ctrl_kmac_err_chk 7.240s 1039.187us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 74.190s 2599.967us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 74.190s 2599.967us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 74.190s 2599.967us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 21.280s 5199.953us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 99.530s 2704.454us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 183.510s 9241.428us 1 1 100.00