Simulation Results: rom_ctrl/64kb

 
22/04/2026 19:39:07 DVSim: v1.32.0 sha: 062f5b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.69 %
  • code
  • 99.36 %
  • assert
  • 96.80 %
  • func
  • 96.90 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 98.07 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.220s 218.823us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 9.090s 2118.735us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.620s 499.036us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.970s 1690.591us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 9.800s 6192.612us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.680s 782.318us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.620s 499.036us 1 1 100.00
rom_ctrl_csr_aliasing 9.800s 6192.612us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.720s 699.832us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.900s 537.161us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 7.850s 913.007us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 30.400s 7194.475us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 19.210s 2142.500us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.220s 212.445us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 9.160s 1113.888us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 9.160s 1113.888us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.090s 2118.735us 1 1 100.00
rom_ctrl_csr_rw 6.620s 499.036us 1 1 100.00
rom_ctrl_csr_aliasing 9.800s 6192.612us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.450s 689.072us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.090s 2118.735us 1 1 100.00
rom_ctrl_csr_rw 6.620s 499.036us 1 1 100.00
rom_ctrl_csr_aliasing 9.800s 6192.612us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.450s 689.072us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 157.100s 14631.870us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 22.810s 2908.257us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 228.920s 1432.275us 1 1 100.00
rom_ctrl_tl_intg_err 50.360s 511.759us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 228.920s 1432.275us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 228.920s 1432.275us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 157.100s 14631.870us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 157.100s 14631.870us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 157.100s 14631.870us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 157.100s 14631.870us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 157.100s 14631.870us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 228.920s 1432.275us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 228.920s 1432.275us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.220s 218.823us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.220s 218.823us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.220s 218.823us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 50.360s 511.759us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 157.100s 14631.870us 1 1 100.00
rom_ctrl_kmac_err_chk 19.210s 2142.500us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 157.100s 14631.870us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 157.100s 14631.870us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 157.100s 14631.870us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 22.810s 2908.257us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 228.920s 1432.275us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 181.220s 3586.707us 1 1 100.00