Simulation Results: rstmgr

 
22/04/2026 19:39:07 DVSim: v1.32.0 sha: 062f5b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.12 %
  • code
  • 99.22 %
  • assert
  • 97.25 %
  • func
  • 91.87 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.75 %
  • toggle
  • 99.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.050s 56.273us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.960s 63.712us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.790s 36.056us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.030s 195.783us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.010s 42.417us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.290s 96.485us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.790s 36.056us 1 1 100.00
rstmgr_csr_aliasing 1.010s 42.417us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.190s 117.981us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.100s 37.988us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.000s 82.520us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.860s 521.375us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.860s 521.375us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.860s 521.375us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.860s 521.375us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 4.580s 667.368us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.920s 36.847us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.260s 81.851us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.260s 81.851us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.960s 63.712us 1 1 100.00
rstmgr_csr_rw 0.790s 36.056us 1 1 100.00
rstmgr_csr_aliasing 1.010s 42.417us 1 1 100.00
rstmgr_same_csr_outstanding 1.080s 43.088us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.960s 63.712us 1 1 100.00
rstmgr_csr_rw 0.790s 36.056us 1 1 100.00
rstmgr_csr_aliasing 1.010s 42.417us 1 1 100.00
rstmgr_same_csr_outstanding 1.080s 43.088us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 16.280s 3517.214us 1 1 100.00
rstmgr_tl_intg_err 2.590s 333.712us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 16.280s 3517.214us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 16.280s 3517.214us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.590s 333.712us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.970s 57.734us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.930s 460.477us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.340s 291.752us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 16.280s 3517.214us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.790s 36.056us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.790s 36.056us 1 1 100.00