Simulation Results

Simulation Results: rv_dm/use_dmi_interface

22/04/2026 19:39:07 DVSim: v1.32.0 sha: 062f5b3 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
72.44 %

code
73.21 %

assert
96.01 %

func
48.11 %

line
90.53 %

branch
75.21 %

cond
76.88 %

toggle
70.29 %

FSM
53.12 %

Validation stages

V1		96.30%
V2		69.57%
V2S		100.00%
V3		0.00%
unmapped		0.00%

26/27 passed

96.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	6.590s	3092.450us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	1.140s	118.331us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	0.880s	226.028us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	26.630s	13895.152us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	1.480s	378.290us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	9.960s	8870.842us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	2.970s	1717.655us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	12.300s	12123.237us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	57.610s	111217.235us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	1.360s	385.560us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	1.020s	705.141us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	1.320s	794.624us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	0.720s	81.194us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	0.860s	86.842us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	5.340s	2445.396us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	0.750s	356.101us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	0.710s	377.524us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	1.360s	385.560us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	0.860s	494.477us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	2.310s	1519.635us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	1.320s	794.624us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	0.990s	157.269us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	1.270s	235.601us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	1.260s	67.987us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	23.600s	2557.847us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	17.480s	697.874us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	2.370s	349.652us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	17.480s	697.874us	1	1	100.00
	rv_dm_csr_rw	1.260s	67.987us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	0.650s	76.250us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	0.960s	152.767us	1	1	100.00

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	6.590s	3092.450us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	1.120s	228.808us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	2.070s	757.368us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	0.720s	199.332us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	2.020s	1202.785us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	515.550s	300000.000us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	505.580s	300000.000us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	129.040s	300000.000us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	131.960s	300000.000us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	0.980s	174.410us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	2.360s	3450.974us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	0.770s	211.575us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	0.920s	259.563us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	11.510s	11800.892us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	37.660s	2146.970us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	1.420s	387.888us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	0.720s	161.474us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	0.710s	95.327us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	3.460s	954.088us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	3.460s	954.088us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	17.480s	697.874us	1	1	100.00
	rv_dm_csr_hw_reset	1.270s	235.601us	1	1	100.00
	rv_dm_csr_rw	1.260s	67.987us	1	1	100.00
	rv_dm_same_csr_outstanding	3.250s	871.552us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	17.480s	697.874us	1	1	100.00
	rv_dm_csr_hw_reset	1.270s	235.601us	1	1	100.00
	rv_dm_csr_rw	1.260s	67.987us	1	1	100.00
	rv_dm_same_csr_outstanding	3.250s	871.552us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	1.740s	373.867us	1	1	100.00
	rv_dm_tl_intg_err	16.120s	2521.482us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	16.120s	2521.482us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	2.360s	3450.974us	1	1	100.00
	rv_dm_debug_disabled	0.850s	103.595us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	2.360s	3450.974us	1	1	100.00
	rv_dm_debug_disabled	0.850s	103.595us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	6.590s	3092.450us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	1.070s	448.923us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	1.090s	92.976us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	1.090s	92.976us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	1.070s	448.923us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	2.120s	138.012us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	337.710s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
	rv_dm_sba_tl_access	28814548008744900693612993317393970661457714180143826921131344759321497701088	86	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	45676853995469843842490155980881554215303442922150778523003258586616515047777	86	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	41193187601925122651329210572220093762250040561315747872513500492253442721053	86	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	45894188006565083147007305263261614647038691122840611397348138372960683342577	86	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_scanmode	2835245994077654620266678184195672651595353023879550169033923005363452022998	77	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 'b (* [] vs [*])
	rv_dm_mem_tl_access_resuming	43071743583842161599995104095740814646772930610780393945950124834362004408552	77	UVM_INFO @ 81193868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	98466019699990915325236313095725603787170779040834591862942101815069943594072	80	UVM_INFO @ 138011532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [] vs [*])
	rv_dm_hart_unavail	66035571897220537676495573594464034081504854595169155595807884836729388150293	77	UVM_INFO @ 259562976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])
	rv_dm_jtag_dmi_debug_disabled	100162711019981561875148210454563081791781541181648782045258262085288152125191	77	UVM_INFO @ 174410097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	30964294847739823537482946899793167040858411160111071839753647419896491397823	78	UVM_INFO @ 161473793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---