Simulation Results: rv_timer

 
22/04/2026 19:39:07 DVSim: v1.32.0 sha: 062f5b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.38 %
  • code
  • 99.74 %
  • assert
  • 96.82 %
  • func
  • 95.59 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 98.97 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.940s 75.130us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.640s 74.776us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.580s 45.723us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.190s 191.279us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.910s 27.688us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.290s 104.478us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.580s 45.723us 1 1 100.00
rv_timer_csr_aliasing 0.910s 27.688us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.780s 102.999us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 0.790s 475.931us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 57.130s 162342.416us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 57.130s 162342.416us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 0.860s 581.909us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.650s 13.875us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.620s 22.121us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.110s 315.699us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.110s 315.699us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.640s 74.776us 1 1 100.00
rv_timer_csr_rw 0.580s 45.723us 1 1 100.00
rv_timer_csr_aliasing 0.910s 27.688us 1 1 100.00
rv_timer_same_csr_outstanding 0.650s 69.372us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.640s 74.776us 1 1 100.00
rv_timer_csr_rw 0.580s 45.723us 1 1 100.00
rv_timer_csr_aliasing 0.910s 27.688us 1 1 100.00
rv_timer_same_csr_outstanding 0.650s 69.372us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.740s 152.440us 1 1 100.00
rv_timer_tl_intg_err 1.240s 139.263us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.240s 139.263us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 0.600s 39.473us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 0.700s 215.573us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 35.890s 6119.154us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 83060021999687444073998866092610885360086335797038508797184125360164319371830 75
UVM_INFO @ 215572685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_random_reset 115205602555055149400487464044255033543405549524451016114514907128677097366419 75
UVM_INFO @ 102998668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---