| V1 |
|
100.00% |
| V2 |
|
92.31% |
| V2S |
|
100.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| spi_device_flash_and_tpm | 276.510s | 125759.131us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| spi_device_csr_hw_reset | 1.120s | 71.062us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| spi_device_csr_rw | 2.020s | 40.776us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| spi_device_csr_bit_bash | 24.200s | 20015.507us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| spi_device_csr_aliasing | 15.110s | 634.447us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| spi_device_csr_mem_rw_with_rand_reset | 1.550s | 176.554us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| spi_device_csr_rw | 2.020s | 40.776us | 1 | 1 | 100.00 | |
| spi_device_csr_aliasing | 15.110s | 634.447us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| spi_device_mem_walk | 0.860s | 92.642us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| spi_device_mem_partial_access | 1.440s | 62.888us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| csb_read | 1 | 1 | 100.00 | |||
| spi_device_csb_read | 0.860s | 22.092us | 1 | 1 | 100.00 | |
| mem_parity | 0 | 1 | 0.00 | |||
| spi_device_mem_parity | 0.930s | 2.427us | 0 | 1 | 0.00 | |
| mem_cfg | 0 | 1 | 0.00 | |||
| spi_device_ram_cfg | 0.840s | 3.680us | 0 | 1 | 0.00 | |
| tpm_read | 1 | 1 | 100.00 | |||
| spi_device_tpm_rw | 4.380s | 357.070us | 1 | 1 | 100.00 | |
| tpm_write | 1 | 1 | 100.00 | |||
| spi_device_tpm_rw | 4.380s | 357.070us | 1 | 1 | 100.00 | |
| tpm_hw_reg | 2 | 2 | 100.00 | |||
| spi_device_tpm_read_hw_reg | 2.830s | 3031.773us | 1 | 1 | 100.00 | |
| spi_device_tpm_sts_read | 0.950s | 102.683us | 1 | 1 | 100.00 | |
| tpm_fully_random_case | 1 | 1 | 100.00 | |||
| spi_device_tpm_all | 29.920s | 39883.965us | 1 | 1 | 100.00 | |
| pass_cmd_filtering | 2 | 2 | 100.00 | |||
| spi_device_pass_cmd_filtering | 7.410s | 15601.459us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 0.920s | 40.574us | 1 | 1 | 100.00 | |
| pass_addr_translation | 2 | 2 | 100.00 | |||
| spi_device_pass_addr_payload_swap | 7.430s | 1992.919us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 0.920s | 40.574us | 1 | 1 | 100.00 | |
| pass_payload_translation | 2 | 2 | 100.00 | |||
| spi_device_pass_addr_payload_swap | 7.430s | 1992.919us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 0.920s | 40.574us | 1 | 1 | 100.00 | |
| cmd_info_slots | 1 | 1 | 100.00 | |||
| spi_device_flash_all | 0.920s | 40.574us | 1 | 1 | 100.00 | |
| cmd_read_status | 2 | 2 | 100.00 | |||
| spi_device_intercept | 4.230s | 2128.542us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 0.920s | 40.574us | 1 | 1 | 100.00 | |
| cmd_read_jedec | 2 | 2 | 100.00 | |||
| spi_device_intercept | 4.230s | 2128.542us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 0.920s | 40.574us | 1 | 1 | 100.00 | |
| cmd_read_sfdp | 2 | 2 | 100.00 | |||
| spi_device_intercept | 4.230s | 2128.542us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 0.920s | 40.574us | 1 | 1 | 100.00 | |
| cmd_fast_read | 2 | 2 | 100.00 | |||
| spi_device_intercept | 4.230s | 2128.542us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 0.920s | 40.574us | 1 | 1 | 100.00 | |
| cmd_read_pipeline | 2 | 2 | 100.00 | |||
| spi_device_intercept | 4.230s | 2128.542us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 0.920s | 40.574us | 1 | 1 | 100.00 | |
| flash_cmd_upload | 1 | 1 | 100.00 | |||
| spi_device_upload | 4.880s | 6375.122us | 1 | 1 | 100.00 | |
| mailbox_command | 1 | 1 | 100.00 | |||
| spi_device_mailbox | 12.980s | 1699.581us | 1 | 1 | 100.00 | |
| mailbox_cross_outside_command | 1 | 1 | 100.00 | |||
| spi_device_mailbox | 12.980s | 1699.581us | 1 | 1 | 100.00 | |
| mailbox_cross_inside_command | 1 | 1 | 100.00 | |||
| spi_device_mailbox | 12.980s | 1699.581us | 1 | 1 | 100.00 | |
| cmd_read_buffer | 2 | 2 | 100.00 | |||
| spi_device_flash_mode | 11.610s | 4750.764us | 1 | 1 | 100.00 | |
| spi_device_read_buffer_direct | 6.210s | 558.933us | 1 | 1 | 100.00 | |
| cmd_dummy_cycle | 2 | 2 | 100.00 | |||
| spi_device_mailbox | 12.980s | 1699.581us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 0.920s | 40.574us | 1 | 1 | 100.00 | |
| quad_spi | 1 | 1 | 100.00 | |||
| spi_device_flash_all | 0.920s | 40.574us | 1 | 1 | 100.00 | |
| dual_spi | 1 | 1 | 100.00 | |||
| spi_device_flash_all | 0.920s | 40.574us | 1 | 1 | 100.00 | |
| 4b_3b_feature | 1 | 1 | 100.00 | |||
| spi_device_cfg_cmd | 1.850s | 37.116us | 1 | 1 | 100.00 | |
| write_enable_disable | 1 | 1 | 100.00 | |||
| spi_device_cfg_cmd | 1.850s | 37.116us | 1 | 1 | 100.00 | |
| TPM_with_flash_or_passthrough_mode | 1 | 1 | 100.00 | |||
| spi_device_flash_and_tpm | 276.510s | 125759.131us | 1 | 1 | 100.00 | |
| tpm_and_flash_trans_with_min_inactive_time | 1 | 1 | 100.00 | |||
| spi_device_flash_and_tpm_min_idle | 127.220s | 83636.566us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| spi_device_stress_all | 42.230s | 12549.213us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| spi_device_alert_test | 0.650s | 47.897us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| spi_device_intr_test | 0.810s | 32.550us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| spi_device_tl_errors | 2.690s | 838.800us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| spi_device_tl_errors | 2.690s | 838.800us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| spi_device_csr_hw_reset | 1.120s | 71.062us | 1 | 1 | 100.00 | |
| spi_device_csr_rw | 2.020s | 40.776us | 1 | 1 | 100.00 | |
| spi_device_csr_aliasing | 15.110s | 634.447us | 1 | 1 | 100.00 | |
| spi_device_same_csr_outstanding | 1.580s | 56.927us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| spi_device_csr_hw_reset | 1.120s | 71.062us | 1 | 1 | 100.00 | |
| spi_device_csr_rw | 2.020s | 40.776us | 1 | 1 | 100.00 | |
| spi_device_csr_aliasing | 15.110s | 634.447us | 1 | 1 | 100.00 | |
| spi_device_same_csr_outstanding | 1.580s | 56.927us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| spi_device_sec_cm | 1.480s | 69.481us | 1 | 1 | 100.00 | |
| spi_device_tl_intg_err | 5.470s | 109.548us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| spi_device_tl_intg_err | 5.470s | 109.548us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| spi_device_flash_mode_ignore_cmds | 60.160s | 5252.361us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) | ||||
| spi_device_mem_parity | 47539296159903615865213067633865300301945796590959601901339783482421329956348 | 76 |
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 2051848 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 2051848 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[912])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
|
|
| UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) | ||||
| spi_device_ram_cfg | 60074474753740031440967675817863875438583889960292213229911818874760254095284 | 76 |
UVM_ERROR @ 1277886 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x9e957c [100111101001010101111100] vs 0x0 [0])
UVM_ERROR @ 1339886 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa1c9d6 [101000011100100111010110] vs 0x0 [0])
UVM_ERROR @ 1409886 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xdd5b0d [110111010101101100001101] vs 0x0 [0])
UVM_ERROR @ 1472886 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x814b68 [100000010100101101101000] vs 0x0 [0])
|
|