Simulation Results: spi_host

 
22/04/2026 19:39:07 DVSim: v1.32.0 sha: 062f5b3 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.11 %
  • code
  • 94.79 %
  • assert
  • 95.45 %
  • func
  • 89.08 %
  • block
  • 96.65 %
  • line
  • 98.49 %
  • branch
  • 92.65 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 52.000s 6113.948us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 56.079us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 2.000s 50.602us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 56.728us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 78.393us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 86.823us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 2.000s 50.602us 1 1 100.00
spi_host_csr_aliasing 1.000s 78.393us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 14.693us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 18.703us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 61.078us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 3.000s 270.647us 1 1 100.00
spi_host_error_cmd 1.000s 48.546us 1 1 100.00
spi_host_event 7.000s 1487.746us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 147.232us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 147.232us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 147.232us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 9.000s 558.184us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 100.623us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 147.232us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 147.232us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 52.000s 6113.948us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 52.000s 6113.948us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 20.000s 4802.923us 1 1 100.00
spien 1 1 100.00
spi_host_spien 4.000s 1276.872us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 67.000s 2204.800us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 3.000s 285.476us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 3.000s 270.647us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 40.472us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 42.517us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 3.000s 131.149us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 3.000s 131.149us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 56.079us 1 1 100.00
spi_host_csr_rw 2.000s 50.602us 1 1 100.00
spi_host_csr_aliasing 1.000s 78.393us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 64.462us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 56.079us 1 1 100.00
spi_host_csr_rw 2.000s 50.602us 1 1 100.00
spi_host_csr_aliasing 1.000s 78.393us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 64.462us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 329.631us 1 1 100.00
spi_host_sec_cm 1.000s 76.680us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 329.631us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 17.000s 838.904us 1 1 100.00