Simulation Results: sram_ctrl/main

 
22/04/2026 19:39:07 DVSim: v1.32.0 sha: 062f5b3 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.84 %
  • code
  • 96.02 %
  • assert
  • 95.91 %
  • func
  • 92.60 %
  • block
  • 95.07 %
  • line
  • 95.77 %
  • branch
  • 92.22 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 1481.329us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 82.913us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 26.144us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 547.792us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 19.154us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 829.566us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 26.144us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 19.154us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 265.000s 296118.553us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 74.000s 1663.466us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 18.000s 16430.499us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 74.000s 9484.364us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 157.000s 56335.996us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 68.000s 124308.419us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 9.000s 2405.282us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 27.000s 19024.880us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 2237.206us 1 1 100.00
sram_ctrl_partial_access_b2b 224.000s 33767.179us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 4.000s 2781.971us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.000s 682.989us 1 1 100.00
sram_ctrl_throughput_w_readback 5.000s 2693.155us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 15.000s 10004.606us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.000s 1404.317us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 312.000s 62112.706us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 15.314us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 79.915us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 79.915us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 82.913us 1 1 100.00
sram_ctrl_csr_rw 1.000s 26.144us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 19.154us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 71.031us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 82.913us 1 1 100.00
sram_ctrl_csr_rw 1.000s 26.144us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 19.154us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 71.031us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 14.000s 3843.903us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 304.556us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 143.671us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 304.556us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 143.671us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 15.000s 10004.606us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 15.000s 10004.606us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 26.144us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 27.000s 19024.880us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 27.000s 19024.880us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 27.000s 19024.880us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 9.000s 2405.282us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 1866.713us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 14.000s 3843.903us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.000s 2775.772us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 1481.329us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 1481.329us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 27.000s 19024.880us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 304.556us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 9.000s 2405.282us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 304.556us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 304.556us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 1481.329us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 304.556us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 15.000s 546.894us 1 1 100.00