Simulation Results: uart

 
22/04/2026 19:39:07 DVSim: v1.32.0 sha: 062f5b3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.32 %
  • code
  • 95.96 %
  • assert
  • 97.12 %
  • func
  • 47.89 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 95.68 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.890s 675.832us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.610s 44.723us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.610s 10.833us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.940s 227.874us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.800s 22.359us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.760s 28.395us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.610s 10.833us 1 1 100.00
uart_csr_aliasing 0.800s 22.359us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 129.430s 100609.452us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.890s 675.832us 1 1 100.00
uart_tx_rx 129.430s 100609.452us 1 1 100.00
parity_error 2 2 100.00
uart_intr 5.510s 37671.791us 1 1 100.00
uart_rx_parity_err 8.560s 9887.205us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 129.430s 100609.452us 1 1 100.00
uart_intr 5.510s 37671.791us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 36.360s 71107.689us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 20.910s 146831.693us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 7.680s 11489.250us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 5.510s 37671.791us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 5.510s 37671.791us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 5.510s 37671.791us 1 1 100.00
perf 1 1 100.00
uart_perf 85.570s 32429.123us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 6.180s 4854.674us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 6.180s 4854.674us 1 1 100.00
rx_noise_filter 1 1 100.00
uart_noise_filter 41.250s 36117.861us 1 1 100.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.960s 3723.441us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.760s 1864.153us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 7.570s 4548.403us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 245.680s 58600.283us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 94.920s 74414.289us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.620s 11.832us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.670s 10.875us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.230s 362.635us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.230s 362.635us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.610s 44.723us 1 1 100.00
uart_csr_rw 0.610s 10.833us 1 1 100.00
uart_csr_aliasing 0.800s 22.359us 1 1 100.00
uart_same_csr_outstanding 0.620s 85.336us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.610s 44.723us 1 1 100.00
uart_csr_rw 0.610s 10.833us 1 1 100.00
uart_csr_aliasing 0.800s 22.359us 1 1 100.00
uart_same_csr_outstanding 0.620s 85.336us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.100s 601.218us 1 1 100.00
uart_tl_intg_err 1.340s 113.189us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.340s 113.189us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 17.980s 17035.840us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *
uart_stress_all_with_rand_reset 15671051640940176080236848966656324374860097374705883779449679096193687691141 125
UVM_ERROR @ 15542715306 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 15543340306 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 15858840306 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 15858840306 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1