Simulation Results: ac_range_check

 
23/04/2026 19:40:15 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.92 %
  • code
  • 93.09 %
  • assert
  • 97.75 %
  • func
  • 57.93 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 81.09 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 29.000s 1553.134us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 40.000s 3322.810us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 3.000s 149.940us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 2.000s 86.455us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 33.000s 8516.329us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 19.000s 1212.873us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 80.487us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 2.000s 86.455us 1 1 100.00
ac_range_check_csr_aliasing 19.000s 1212.873us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 3.000s 82.666us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 24.000s 1212.112us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 125.000s 30108.518us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 2.000s 33.645us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 1.000s 49.160us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 3.000s 97.792us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 3.000s 97.792us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 3.000s 149.940us 1 1 100.00
ac_range_check_csr_rw 2.000s 86.455us 1 1 100.00
ac_range_check_csr_aliasing 19.000s 1212.873us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 156.492us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 3.000s 149.940us 1 1 100.00
ac_range_check_csr_rw 2.000s 86.455us 1 1 100.00
ac_range_check_csr_aliasing 19.000s 1212.873us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 156.492us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 9.000s 972.886us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 9.000s 972.886us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 9.000s 972.886us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 9.000s 972.886us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 64.000s 1431.865us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 1.000s 35.790us 1 1 100.00
ac_range_check_tl_intg_err 7.000s 3782.304us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 262.000s 4289.932us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 28.000s 1167.969us 1 1 100.00