Simulation Results: aes/masked

 
23/04/2026 19:40:15 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.98 %
  • code
  • 95.13 %
  • assert
  • 98.29 %
  • func
  • 64.53 %
  • block
  • 95.77 %
  • line
  • 97.54 %
  • branch
  • 89.54 %
  • toggle
  • 97.96 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
89.47%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 78.262us 1 1 100.00
smoke 1 1 100.00
aes_smoke 4.000s 98.794us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 118.612us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 71.407us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 8.000s 1756.127us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 215.843us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 81.905us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 71.407us 1 1 100.00
aes_csr_aliasing 3.000s 215.843us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 4.000s 98.794us 1 1 100.00
aes_config_error 3.000s 251.475us 1 1 100.00
aes_stress 4.000s 133.071us 1 1 100.00
key_length 3 3 100.00
aes_smoke 4.000s 98.794us 1 1 100.00
aes_config_error 3.000s 251.475us 1 1 100.00
aes_stress 4.000s 133.071us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 133.071us 1 1 100.00
aes_b2b 14.000s 253.838us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 133.071us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 4.000s 98.794us 1 1 100.00
aes_config_error 3.000s 251.475us 1 1 100.00
aes_stress 4.000s 133.071us 1 1 100.00
aes_alert_reset 31.000s 10020.785us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 68.087us 1 1 100.00
aes_config_error 3.000s 251.475us 1 1 100.00
aes_alert_reset 31.000s 10020.785us 0 1 0.00
trigger_clear_test 0 1 0.00
aes_clear 3.000s 237.223us 0 1 0.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 11.000s 525.338us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 6.000s 1047.111us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 31.000s 10020.785us 0 1 0.00
stress 1 1 100.00
aes_stress 4.000s 133.071us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 133.071us 1 1 100.00
aes_sideload 3.000s 62.728us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 227.762us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 6.000s 342.246us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 76.018us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 3.000s 112.877us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 941.034us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 941.034us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 118.612us 1 1 100.00
aes_csr_rw 2.000s 71.407us 1 1 100.00
aes_csr_aliasing 3.000s 215.843us 1 1 100.00
aes_same_csr_outstanding 2.000s 272.248us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 118.612us 1 1 100.00
aes_csr_rw 2.000s 71.407us 1 1 100.00
aes_csr_aliasing 3.000s 215.843us 1 1 100.00
aes_same_csr_outstanding 2.000s 272.248us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 204.746us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 12.000s 10057.671us 0 1 0.00
aes_control_fi 3.000s 58.313us 1 1 100.00
aes_cipher_fi 3.000s 179.916us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 142.314us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 142.314us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 142.314us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 142.314us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 188.062us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 8.000s 2104.750us 1 1 100.00
aes_tl_intg_err 3.000s 330.127us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 330.127us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 31.000s 10020.785us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 142.314us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 142.314us 1 1 100.00
sec_cm_main_config_sparse 2 4 50.00
aes_smoke 4.000s 98.794us 1 1 100.00
aes_stress 4.000s 133.071us 1 1 100.00
aes_alert_reset 31.000s 10020.785us 0 1 0.00
aes_core_fi 37.000s 10029.566us 0 1 0.00
sec_cm_gcm_config_sparse 3 4 75.00
aes_gcm_save_restore 3.000s 76.018us 1 1 100.00
aes_config_error 3.000s 251.475us 1 1 100.00
aes_stress 4.000s 133.071us 1 1 100.00
aes_core_fi 37.000s 10029.566us 0 1 0.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 142.314us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 56.262us 1 1 100.00
aes_stress 4.000s 133.071us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 133.071us 1 1 100.00
aes_sideload 3.000s 62.728us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 56.262us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 56.262us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 56.262us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 56.262us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 56.262us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 133.071us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 133.071us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 12.000s 10057.671us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 12.000s 10057.671us 0 1 0.00
aes_control_fi 3.000s 58.313us 1 1 100.00
aes_cipher_fi 3.000s 179.916us 1 1 100.00
aes_ctr_fi 3.000s 59.835us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 12.000s 10057.671us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 12.000s 10057.671us 0 1 0.00
aes_control_fi 3.000s 58.313us 1 1 100.00
aes_cipher_fi 3.000s 179.916us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 179.916us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 12.000s 10057.671us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 12.000s 10057.671us 0 1 0.00
aes_control_fi 3.000s 58.313us 1 1 100.00
aes_ctr_fi 3.000s 59.835us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 12.000s 10057.671us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 12.000s 10057.671us 0 1 0.00
aes_control_fi 3.000s 58.313us 1 1 100.00
aes_cipher_fi 3.000s 179.916us 1 1 100.00
aes_ctr_fi 3.000s 59.835us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 31.000s 10020.785us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 12.000s 10057.671us 0 1 0.00
aes_control_fi 3.000s 58.313us 1 1 100.00
aes_cipher_fi 3.000s 179.916us 1 1 100.00
aes_ctr_fi 3.000s 59.835us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 12.000s 10057.671us 0 1 0.00
aes_control_fi 3.000s 58.313us 1 1 100.00
aes_cipher_fi 3.000s 179.916us 1 1 100.00
aes_ctr_fi 3.000s 59.835us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 12.000s 10057.671us 0 1 0.00
aes_control_fi 3.000s 58.313us 1 1 100.00
aes_ctr_fi 3.000s 59.835us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 12.000s 10057.671us 0 1 0.00
aes_ghash_fi 2.000s 106.378us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 12.000s 10057.671us 0 1 0.00
aes_control_fi 3.000s 58.313us 1 1 100.00
aes_cipher_fi 3.000s 179.916us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 3.000s 68.373us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:775) scoreboard [scoreboard] # *
aes_clear 32978450003344707617868888976608397831833007492596990793362354833544643745787 2444
TEST FAILED MESSAGES DID NOT MATCH
0 ba 77 0e 0
1 72 f7 12 0
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred!
aes_alert_reset 51531956323303449848309314402152232202097537316330811912669491785361694440781 422
UVM_INFO @ 10020784886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred!
aes_fi 21260093126893820813038669472961346832968644935193168005839304940442377646302 3338
UVM_INFO @ 10057671167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_core_fi_vseq] wait timeout occurred!
aes_core_fi 62894601934144884205250930520845708551188498130751348900861566308198036854540 140
UVM_INFO @ 10029566294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:75) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 49813722026507652687595580540961302492412479916952903686080260872327622064823 174
UVM_INFO @ 68372987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---