Simulation Results: aes/unmasked

 
23/04/2026 19:40:15 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.07 %
  • code
  • 91.42 %
  • assert
  • 97.75 %
  • func
  • 66.05 %
  • block
  • 91.00 %
  • line
  • 93.17 %
  • branch
  • 83.75 %
  • toggle
  • 97.99 %
  • FSM
  • 90.78 %
Validation stages
V1
100.00%
V2
94.74%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 105.203us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 93.160us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 118.972us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 57.295us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 322.453us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 594.309us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 141.070us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 57.295us 1 1 100.00
aes_csr_aliasing 3.000s 594.309us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 93.160us 1 1 100.00
aes_config_error 2.000s 63.806us 1 1 100.00
aes_stress 3.000s 243.913us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 93.160us 1 1 100.00
aes_config_error 2.000s 63.806us 1 1 100.00
aes_stress 3.000s 243.913us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 243.913us 1 1 100.00
aes_b2b 3.000s 140.269us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 243.913us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 93.160us 1 1 100.00
aes_config_error 2.000s 63.806us 1 1 100.00
aes_stress 3.000s 243.913us 1 1 100.00
aes_alert_reset 3.000s 121.094us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 1.000s 101.938us 1 1 100.00
aes_config_error 2.000s 63.806us 1 1 100.00
aes_alert_reset 3.000s 121.094us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 151.716us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 813.732us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 4.000s 276.198us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 121.094us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 243.913us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 243.913us 1 1 100.00
aes_sideload 2.000s 103.437us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 108.674us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 7.000s 10810.148us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 2.000s 65.466us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 53.978us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 566.531us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 566.531us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 118.972us 1 1 100.00
aes_csr_rw 2.000s 57.295us 1 1 100.00
aes_csr_aliasing 3.000s 594.309us 1 1 100.00
aes_same_csr_outstanding 2.000s 104.935us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 118.972us 1 1 100.00
aes_csr_rw 2.000s 57.295us 1 1 100.00
aes_csr_aliasing 3.000s 594.309us 1 1 100.00
aes_same_csr_outstanding 2.000s 104.935us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 88.580us 1 1 100.00
fault_inject 1 3 33.33
aes_fi 29.000s 10025.362us 0 1 0.00
aes_control_fi 3.000s 52.741us 1 1 100.00
aes_cipher_fi 40.000s 200000.000us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 92.710us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 92.710us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 92.710us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 92.710us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 87.378us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 584.735us 1 1 100.00
aes_tl_intg_err 1.000s 200.334us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 1.000s 200.334us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 121.094us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 92.710us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 92.710us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 93.160us 1 1 100.00
aes_stress 3.000s 243.913us 1 1 100.00
aes_alert_reset 3.000s 121.094us 1 1 100.00
aes_core_fi 2.000s 107.862us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 2.000s 65.466us 1 1 100.00
aes_config_error 2.000s 63.806us 1 1 100.00
aes_stress 3.000s 243.913us 1 1 100.00
aes_core_fi 2.000s 107.862us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 92.710us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 57.788us 1 1 100.00
aes_stress 3.000s 243.913us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 243.913us 1 1 100.00
aes_sideload 2.000s 103.437us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 57.788us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 57.788us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 57.788us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 57.788us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 57.788us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 243.913us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 243.913us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 29.000s 10025.362us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 29.000s 10025.362us 0 1 0.00
aes_control_fi 3.000s 52.741us 1 1 100.00
aes_cipher_fi 40.000s 200000.000us 0 1 0.00
aes_ctr_fi 2.000s 53.445us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 29.000s 10025.362us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 29.000s 10025.362us 0 1 0.00
aes_control_fi 3.000s 52.741us 1 1 100.00
aes_cipher_fi 40.000s 200000.000us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 40.000s 200000.000us 0 1 0.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 29.000s 10025.362us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 29.000s 10025.362us 0 1 0.00
aes_control_fi 3.000s 52.741us 1 1 100.00
aes_ctr_fi 2.000s 53.445us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 29.000s 10025.362us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 29.000s 10025.362us 0 1 0.00
aes_control_fi 3.000s 52.741us 1 1 100.00
aes_cipher_fi 40.000s 200000.000us 0 1 0.00
aes_ctr_fi 2.000s 53.445us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 121.094us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 29.000s 10025.362us 0 1 0.00
aes_control_fi 3.000s 52.741us 1 1 100.00
aes_cipher_fi 40.000s 200000.000us 0 1 0.00
aes_ctr_fi 2.000s 53.445us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 29.000s 10025.362us 0 1 0.00
aes_control_fi 3.000s 52.741us 1 1 100.00
aes_cipher_fi 40.000s 200000.000us 0 1 0.00
aes_ctr_fi 2.000s 53.445us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 29.000s 10025.362us 0 1 0.00
aes_control_fi 3.000s 52.741us 1 1 100.00
aes_ctr_fi 2.000s 53.445us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 29.000s 10025.362us 0 1 0.00
aes_ghash_fi 2.000s 56.982us 1 1 100.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 29.000s 10025.362us 0 1 0.00
aes_control_fi 3.000s 52.741us 1 1 100.00
aes_cipher_fi 40.000s 200000.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 61.185us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred!
aes_fi 4628270149490025648079612828165422937997191971774670886517831956488005358838 2177
UVM_INFO @ 10025361815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
aes_cipher_fi 107551015279855689342393221372350778223729639847497192290400573860883662754528 158
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred!
aes_stress_all 11149646645686375846632888292384137891274460279377077975833774063389481662267 4244
UVM_INFO @ 10810148252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
aes_stress_all_with_rand_reset 38006076852471258178272558047997981853633138896482306760833443195672072486695 200
UVM_INFO @ 61185299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---