Simulation Results: alert_handler

 
23/04/2026 19:40:15 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.00 %
  • code
  • 93.01 %
  • assert
  • 98.11 %
  • func
  • 78.89 %
  • line
  • 99.78 %
  • branch
  • 98.29 %
  • cond
  • 90.63 %
  • toggle
  • 94.08 %
  • FSM
  • 82.26 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 26.910s 2628.875us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 3.250s 93.484us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 7.470s 486.942us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 424.830s 9873.841us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 88.150s 7484.214us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 6.440s 662.983us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 7.470s 486.942us 1 1 100.00
alert_handler_csr_aliasing 88.150s 7484.214us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 177.930s 4064.907us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 21.660s 285.535us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 2479.080s 118940.071us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 7.000s 1219.318us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 26.910s 2628.875us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 18.810s 1457.467us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 33.720s 3842.415us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 279.190s 36847.070us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 996.910s 29570.833us 1 1 100.00
alert_handler_lpg_stub_clk 1979.530s 391822.151us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 1760.940s 68649.386us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 12.160s 1542.064us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 3.340s 132.247us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.620s 6.413us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 3.230s 28.584us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 3.230s 28.584us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 3.250s 93.484us 1 1 100.00
alert_handler_csr_rw 7.470s 486.942us 1 1 100.00
alert_handler_csr_aliasing 88.150s 7484.214us 1 1 100.00
alert_handler_same_csr_outstanding 29.350s 2291.426us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 3.250s 93.484us 1 1 100.00
alert_handler_csr_rw 7.470s 486.942us 1 1 100.00
alert_handler_csr_aliasing 88.150s 7484.214us 1 1 100.00
alert_handler_same_csr_outstanding 29.350s 2291.426us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 228.910s 4277.826us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 228.910s 4277.826us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 228.910s 4277.826us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 228.910s 4277.826us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 394.460s 19163.269us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 9.920s 1146.421us 1 1 100.00
alert_handler_tl_intg_err 36.930s 1353.039us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 36.930s 1353.039us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 228.910s 4277.826us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 26.910s 2628.875us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 26.910s 2628.875us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 26.910s 2628.875us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 26.910s 2628.875us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 7.000s 1219.318us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 996.910s 29570.833us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 7.000s 1219.318us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2479.080s 118940.071us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2479.080s 118940.071us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 9.920s 1146.421us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 9.920s 1146.421us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 9.920s 1146.421us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 9.920s 1146.421us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 9.920s 1146.421us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.920s 1146.421us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.920s 1146.421us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.920s 1146.421us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 9.920s 1146.421us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 61.050s 3931.062us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state
alert_handler_ping_timeout 44363495902200982195488317206633940087875875660758093926377930819955763344422 139
UVM_INFO @ 36847070279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
alert_handler_stress_all_with_rand_reset 64030763756984987138146867840504610996211129951884706812001254991230430080585 107
UVM_INFO @ 3931062335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---