Simulation Results: clkmgr

 
23/04/2026 19:40:15 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.87 %
  • code
  • 69.18 %
  • assert
  • 89.26 %
  • func
  • 60.16 %
  • line
  • 82.11 %
  • branch
  • 87.42 %
  • cond
  • 77.13 %
  • toggle
  • 99.25 %
  • FSM
  • 0.00 %
Validation stages
V1
33.33%
V2
53.85%
V2S
37.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.910s 18.887us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 2.070s 207.882us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.580s 2.657us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 4.160s 381.818us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.870s 11.342us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.870s 16.236us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.580s 2.657us 0 1 0.00
clkmgr_csr_aliasing 0.870s 11.342us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.920s 40.639us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.090s 49.530us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.000s 51.610us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.910s 18.887us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.640s 5.497us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.620s 4.131us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.640s 5.497us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 1.170s 33.273us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.350s 82.587us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.150s 24.626us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.150s 24.626us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 2.070s 207.882us 1 1 100.00
clkmgr_csr_rw 0.580s 2.657us 0 1 0.00
clkmgr_csr_aliasing 0.870s 11.342us 0 1 0.00
clkmgr_same_csr_outstanding 0.770s 12.659us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 2.070s 207.882us 1 1 100.00
clkmgr_csr_rw 0.580s 2.657us 0 1 0.00
clkmgr_csr_aliasing 0.870s 11.342us 0 1 0.00
clkmgr_same_csr_outstanding 0.770s 12.659us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 6.940s 734.703us 1 1 100.00
clkmgr_tl_intg_err 0.840s 32.951us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.400s 102.352us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.400s 102.352us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.400s 102.352us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.400s 102.352us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.660s 9.838us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.840s 32.951us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.640s 5.497us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.620s 4.131us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.400s 102.352us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.920s 46.770us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.580s 2.657us 0 1 0.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 6.940s 734.703us 1 1 100.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.580s 2.657us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.580s 2.657us 0 1 0.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 6.940s 734.703us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.600s 5.058us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.070s 42.206us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b*
clkmgr_frequency 108569281266639677964038035612914652445463558798957457232402051238166459915939 75
UVM_INFO @ 5497336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 109197322559967672246697518620802450386328265370036815445332803758340399571303 78
UVM_INFO @ 42206244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 19351367702624439619455120788340279432762430693015869306357517646109320781303 108
UVM_INFO @ 33272644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b*
clkmgr_frequency_timeout 47234146534417396104473270876538476070615562968785521909640194306115606001801 78
UVM_INFO @ 4130666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en
clkmgr_regwen 3606893300719574578872912160426265812110751694196590778402923838421196298453 74
UVM_INFO @ 5058281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: *
clkmgr_shadow_reg_errors_with_csr_rw 92118135912945168506011622119679386210749848498618834032286574838417850418608 75
UVM_INFO @ 9838375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 26018746463614305650989725571439310788922935606299978489314504050387247459348 78
UVM_INFO @ 32951435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: *
clkmgr_csr_rw 111641546228271860437952818437698055790020160999926119477799178168399812236754 75
UVM_INFO @ 2656663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 30761532668316835060102693251757952248321417072069451996939045037906637607712 75
UVM_INFO @ 11342007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 16767862553161902529971450762646413782464693997907244000026549315192515507616 82
UVM_INFO @ 16235960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: *
clkmgr_csr_bit_bash 20679566841865399375917665027567399706169010243393453580763424160896743981615 75
UVM_INFO @ 381817916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:649) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
clkmgr_same_csr_outstanding 36625906366933241208494930113710536628048321054637045515553209818879990922135 75
UVM_INFO @ 12659420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---