Simulation Results: dma

 
23/04/2026 19:40:15 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.64 %
  • code
  • 92.20 %
  • assert
  • 95.55 %
  • func
  • 63.16 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 284.153us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 4.000s 525.986us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 308.001us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 211.908us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 58.724us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 12.000s 4962.465us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 5.000s 319.732us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 91.424us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 58.724us 1 1 100.00
dma_csr_aliasing 5.000s 319.732us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 47.000s 3410.533us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 1082.000s 465855.293us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 97.000s 52340.831us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 97.000s 52340.831us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 1082.000s 465855.293us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 277.000s 115777.515us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 97.000s 52340.831us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 10.000s 1355.397us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 225.000s 123332.718us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 33.111us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 13.707us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 47.705us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 47.705us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 211.908us 1 1 100.00
dma_csr_rw 2.000s 58.724us 1 1 100.00
dma_csr_aliasing 5.000s 319.732us 1 1 100.00
dma_same_csr_outstanding 1.000s 22.848us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 211.908us 1 1 100.00
dma_csr_rw 2.000s 58.724us 1 1 100.00
dma_csr_aliasing 5.000s 319.732us 1 1 100.00
dma_same_csr_outstanding 1.000s 22.848us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 13.000s 270.853us 1 1 100.00
dma_generic_stress 277.000s 115777.515us 1 1 100.00
dma_handshake_stress 97.000s 52340.831us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 7.000s 845.721us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 4.000s 466.971us 1 1 100.00
dma_sec_cm 1.000s 11.623us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 95.000s 10155.899us 1 1 100.00
dma_longer_transfer 5.000s 332.064us 1 1 100.00
dma_stress_all_with_rand_reset 21.000s 1100.518us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 90340598608737161072514635208172404540739420983722945276025647069544703427829 139
UVM_INFO @ 1100517814ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---