Simulation Results: edn/edn0

 
23/04/2026 19:40:15 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.47 %
  • code
  • 77.81 %
  • assert
  • 95.01 %
  • func
  • 77.58 %
  • line
  • 96.85 %
  • branch
  • 89.26 %
  • cond
  • 83.63 %
  • toggle
  • 71.44 %
  • FSM
  • 47.85 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.890s 134.686us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.160s 22.828us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.830s 50.222us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.910s 97.605us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.960s 377.775us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.230s 18.034us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.830s 50.222us 1 1 100.00
edn_csr_aliasing 1.960s 377.775us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.200s 40.994us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.200s 40.994us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.200s 40.994us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.830s 32.677us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.000s 47.758us 1 1 100.00
errs 1 1 100.00
edn_err 0.970s 38.553us 1 1 100.00
disable 2 2 100.00
edn_disable 0.920s 87.565us 1 1 100.00
edn_disable_auto_req_mode 1.120s 49.408us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.870s 553.482us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.840s 39.468us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.020s 55.418us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.530s 42.016us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.530s 42.016us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.160s 22.828us 1 1 100.00
edn_csr_rw 0.830s 50.222us 1 1 100.00
edn_csr_aliasing 1.960s 377.775us 1 1 100.00
edn_same_csr_outstanding 1.300s 135.108us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.160s 22.828us 1 1 100.00
edn_csr_rw 0.830s 50.222us 1 1 100.00
edn_csr_aliasing 1.960s 377.775us 1 1 100.00
edn_same_csr_outstanding 1.300s 135.108us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 7.070s 1538.942us 1 1 100.00
edn_tl_intg_err 1.250s 60.379us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.050s 19.256us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.000s 47.758us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.070s 1538.942us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.070s 1538.942us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.070s 1538.942us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.070s 1538.942us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.000s 47.758us 1 1 100.00
edn_sec_cm 7.070s 1538.942us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.000s 47.758us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.250s 60.379us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 17.210s 1127.011us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 31371364897866073637674241507438880596198528111078947594445828262821237426373 135
UVM_INFO @ 1127010907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---