Simulation Results: edn/edn1

 
23/04/2026 19:40:15 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.01 %
  • code
  • 76.52 %
  • assert
  • 97.14 %
  • func
  • 78.36 %
  • line
  • 96.28 %
  • branch
  • 87.45 %
  • cond
  • 84.08 %
  • toggle
  • 82.99 %
  • FSM
  • 31.82 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.850s 25.571us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.050s 16.588us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.830s 14.617us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.570s 344.420us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.220s 74.804us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.180s 388.624us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.830s 14.617us 1 1 100.00
edn_csr_aliasing 1.220s 74.804us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.160s 41.487us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.160s 41.487us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.160s 41.487us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.950s 26.754us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.960s 28.455us 1 1 100.00
errs 1 1 100.00
edn_err 1.010s 24.631us 1 1 100.00
disable 1 2 50.00
edn_disable 0.830s 21.285us 1 1 100.00
edn_disable_auto_req_mode 1.270s 500.000us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 3.040s 456.385us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.790s 23.028us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.870s 15.995us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.530s 87.340us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.530s 87.340us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.050s 16.588us 1 1 100.00
edn_csr_rw 0.830s 14.617us 1 1 100.00
edn_csr_aliasing 1.220s 74.804us 1 1 100.00
edn_same_csr_outstanding 0.930s 19.576us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.050s 16.588us 1 1 100.00
edn_csr_rw 0.830s 14.617us 1 1 100.00
edn_csr_aliasing 1.220s 74.804us 1 1 100.00
edn_same_csr_outstanding 0.930s 19.576us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.930s 693.273us 1 1 100.00
edn_tl_intg_err 1.350s 50.053us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.780s 28.669us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.960s 28.455us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.930s 693.273us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.930s 693.273us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.930s 693.273us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.930s 693.273us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.960s 28.455us 1 1 100.00
edn_sec_cm 3.930s 693.273us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.960s 28.455us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.350s 50.053us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 46.620s 2965.378us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
edn_disable_auto_req_mode 101933174384342650915561029648644351830774124037114638779238982781340341890375 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---