Simulation Results: hmac

 
23/04/2026 19:40:15 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.10 %
  • code
  • 97.94 %
  • assert
  • 97.80 %
  • func
  • 44.55 %
  • line
  • 99.69 %
  • branch
  • 99.34 %
  • cond
  • 96.57 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 2.300s 134.956us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.960s 108.123us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.940s 111.392us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.170s 115.227us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.160s 457.885us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.520s 99.491us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.940s 111.392us 1 1 100.00
hmac_csr_aliasing 6.160s 457.885us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 13.650s 284.871us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 31.210s 879.371us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 9.350s 733.677us 1 1 100.00
hmac_test_sha384_vectors 20.630s 215.335us 1 1 100.00
hmac_test_sha512_vectors 318.110s 152510.647us 1 1 100.00
hmac_test_hmac256_vectors 10.600s 325.063us 1 1 100.00
hmac_test_hmac384_vectors 7.690s 531.711us 1 1 100.00
hmac_test_hmac512_vectors 7.940s 231.857us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 9.810s 908.809us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 159.840s 1229.621us 1 1 100.00
error 1 1 100.00
hmac_error 8.970s 3208.267us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 24.010s 1969.142us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 2.300s 134.956us 1 1 100.00
hmac_long_msg 13.650s 284.871us 1 1 100.00
hmac_back_pressure 31.210s 879.371us 1 1 100.00
hmac_datapath_stress 159.840s 1229.621us 1 1 100.00
hmac_burst_wr 9.810s 908.809us 1 1 100.00
hmac_stress_all 109.800s 19569.771us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 2.300s 134.956us 1 1 100.00
hmac_long_msg 13.650s 284.871us 1 1 100.00
hmac_back_pressure 31.210s 879.371us 1 1 100.00
hmac_datapath_stress 159.840s 1229.621us 1 1 100.00
hmac_wipe_secret 24.010s 1969.142us 1 1 100.00
hmac_test_sha256_vectors 9.350s 733.677us 1 1 100.00
hmac_test_sha384_vectors 20.630s 215.335us 1 1 100.00
hmac_test_sha512_vectors 318.110s 152510.647us 1 1 100.00
hmac_test_hmac256_vectors 10.600s 325.063us 1 1 100.00
hmac_test_hmac384_vectors 7.690s 531.711us 1 1 100.00
hmac_test_hmac512_vectors 7.940s 231.857us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 2.300s 134.956us 1 1 100.00
hmac_long_msg 13.650s 284.871us 1 1 100.00
hmac_back_pressure 31.210s 879.371us 1 1 100.00
hmac_datapath_stress 159.840s 1229.621us 1 1 100.00
hmac_burst_wr 9.810s 908.809us 1 1 100.00
hmac_error 8.970s 3208.267us 1 1 100.00
hmac_wipe_secret 24.010s 1969.142us 1 1 100.00
hmac_test_sha256_vectors 9.350s 733.677us 1 1 100.00
hmac_test_sha384_vectors 20.630s 215.335us 1 1 100.00
hmac_test_sha512_vectors 318.110s 152510.647us 1 1 100.00
hmac_test_hmac256_vectors 10.600s 325.063us 1 1 100.00
hmac_test_hmac384_vectors 7.690s 531.711us 1 1 100.00
hmac_test_hmac512_vectors 7.940s 231.857us 1 1 100.00
hmac_stress_all 109.800s 19569.771us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 109.800s 19569.771us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.620s 16.944us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.850s 16.176us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.340s 178.931us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.340s 178.931us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.960s 108.123us 1 1 100.00
hmac_csr_rw 0.940s 111.392us 1 1 100.00
hmac_csr_aliasing 6.160s 457.885us 1 1 100.00
hmac_same_csr_outstanding 1.560s 34.169us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.960s 108.123us 1 1 100.00
hmac_csr_rw 0.940s 111.392us 1 1 100.00
hmac_csr_aliasing 6.160s 457.885us 1 1 100.00
hmac_same_csr_outstanding 1.560s 34.169us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.290s 93.228us 1 1 100.00
hmac_tl_intg_err 2.550s 378.900us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.550s 378.900us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 2.300s 134.956us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.250s 53.089us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 74.690s 1829.075us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.950s 57.560us 1 1 100.00