Simulation Results

Simulation Results: i2c

23/04/2026 19:40:15 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.54 %

code
81.57 %

assert
96.19 %

func
78.86 %

line
96.07 %

branch
91.98 %

cond
85.49 %

toggle
89.66 %

FSM
44.64 %

Validation stages

V1		100.00%
V2		90.24%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	18.410s	5632.842us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	6.610s	1282.551us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.700s	19.230us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.840s	27.056us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.730s	454.330us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.770s	41.909us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.020s	25.339us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.840s	27.056us	1	1	100.00
	i2c_csr_aliasing	1.770s	41.909us	1	1	100.00

37/41 passed

90.24 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				1	1	100.00
	i2c_host_error_intr	2.250s	668.865us	1	1	100.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	1.440s	88.017us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	98.050s	12756.582us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.780s	28.892us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	209.950s	4460.369us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	26.780s	3091.228us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.000s	1430.388us	1	1	100.00
	i2c_host_fifo_fmt_empty	7.550s	1783.977us	1	1	100.00
	i2c_host_fifo_reset_rx	2.290s	568.412us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	93.100s	2329.551us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	14.920s	1718.729us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	0.910s	48.751us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.270s	1060.795us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	48.640s	88791.058us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.210s	2575.241us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	39.220s	4823.059us	1	1	100.00
	i2c_target_intr_smoke	3.540s	780.289us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.780s	262.364us	1	1	100.00
	i2c_target_fifo_reset_tx	1.200s	217.064us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	10.790s	23009.626us	1	1	100.00
	i2c_target_stress_rd	39.220s	4823.059us	1	1	100.00
	i2c_target_intr_stress_wr	202.640s	17775.437us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.370s	3878.436us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	11.760s	1069.201us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.660s	2233.355us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	21.080s	10015.200us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.970s	2224.982us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.150s	483.379us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	98.050s	12756.582us	1	1	100.00
	i2c_host_perf_precise	1.370s	98.579us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	14.920s	1718.729us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	3.840s	359.344us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	2.160s	569.922us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.650s	5052.308us	1	1	100.00
	i2c_target_nack_txstretch	1.570s	286.487us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	13.880s	1837.258us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.400s	357.740us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.890s	58.778us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.780s	28.706us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.130s	167.901us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.130s	167.901us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.700s	19.230us	1	1	100.00
	i2c_csr_rw	0.840s	27.056us	1	1	100.00
	i2c_csr_aliasing	1.770s	41.909us	1	1	100.00
	i2c_same_csr_outstanding	1.270s	27.382us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.700s	19.230us	1	1	100.00
	i2c_csr_rw	0.840s	27.056us	1	1	100.00
	i2c_csr_aliasing	1.770s	41.909us	1	1	100.00
	i2c_same_csr_outstanding	1.270s	27.382us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.650s	231.221us	1	1	100.00
	i2c_sec_cm	1.160s	75.494us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.650s	231.221us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	6.020s	549.514us	1
target_error_intr				1
	i2c_target_unexp_stop	1.330s	63.741us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	25.420s	947.788us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
	i2c_host_stress_all	107969773884285717418428520777301569658665503710620893212029116785768212021541	92	UVM_INFO @ 88017395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
	i2c_target_glitch	87670877442702660788319518557126036998060978896878824407545277504431255192521	84	UVM_INFO @ 1060794844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])
	i2c_target_unexp_stop	84139823752917653337846666354164475179969639544204289828513399109423984414911	78	UVM_INFO @ 63740696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
	i2c_target_hrst	89984750826220110721849524220376279216112953526264605826670685410017782245218	79	UVM_INFO @ 10015199945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	i2c_host_stress_all_with_rand_reset	114436152898818683360778471539220341316559927541002455929348197482043421055400	89	UVM_INFO @ 549514128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	21515767179068338789866443484765211428082686417913180618319259691679476169753	100	UVM_INFO @ 947787998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Error-[NOA] Null object access
	i2c_host_mode_toggle	45142548723919462395113123439188935853600594466998244394095635555744272128973	86	src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584 The object at dereference depth 0 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.