Simulation Results: kmac/masked

 
23/04/2026 19:40:15 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.92 %
  • code
  • 90.23 %
  • assert
  • 97.98 %
  • func
  • 93.55 %
  • line
  • 98.82 %
  • branch
  • 96.43 %
  • cond
  • 93.07 %
  • toggle
  • 99.46 %
  • FSM
  • 63.38 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 5.280s 371.884us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.100s 84.279us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.150s 160.858us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 11.530s 576.751us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 6.710s 805.491us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 2.060s 167.819us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.150s 160.858us 1 1 100.00
kmac_csr_aliasing 6.710s 805.491us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.990s 77.681us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.570s 42.802us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 2049.000s 26098.226us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 826.020s 88172.370us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 34.240s 11041.682us 1 1 100.00
kmac_test_vectors_sha3_256 1802.590s 230591.338us 1 1 100.00
kmac_test_vectors_sha3_384 1248.960s 46453.345us 1 1 100.00
kmac_test_vectors_sha3_512 1053.780s 529357.171us 1 1 100.00
kmac_test_vectors_shake_128 114.550s 3435.294us 1 1 100.00
kmac_test_vectors_shake_256 98.970s 26931.470us 1 1 100.00
kmac_test_vectors_kmac 2.760s 285.656us 1 1 100.00
kmac_test_vectors_kmac_xof 2.720s 1552.897us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 135.660s 5541.734us 1 1 100.00
app 1 1 100.00
kmac_app 129.690s 7994.733us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 239.940s 12225.468us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 39.330s 6449.657us 1 1 100.00
error 1 1 100.00
kmac_error 190.960s 7966.730us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 7.490s 5567.319us 1 1 100.00
sideload_invalid 1 1 100.00
kmac_sideload_invalid 4.100s 197.015us 1 1 100.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 25.550s 1367.303us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 23.400s 542.530us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 16.180s 2033.176us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.290s 43.435us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 150.600s 6345.637us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.970s 25.981us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.860s 33.213us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.790s 32.524us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.790s 32.524us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.100s 84.279us 1 1 100.00
kmac_csr_rw 1.150s 160.858us 1 1 100.00
kmac_csr_aliasing 6.710s 805.491us 1 1 100.00
kmac_same_csr_outstanding 1.360s 23.750us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.100s 84.279us 1 1 100.00
kmac_csr_rw 1.150s 160.858us 1 1 100.00
kmac_csr_aliasing 6.710s 805.491us 1 1 100.00
kmac_same_csr_outstanding 1.360s 23.750us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.660s 73.102us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.660s 73.102us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.660s 73.102us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.660s 73.102us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 4.130s 476.209us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 98.420s 97356.941us 1 1 100.00
kmac_tl_intg_err 2.220s 76.755us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.220s 76.755us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.290s 43.435us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 5.280s 371.884us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 135.660s 5541.734us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.660s 73.102us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 98.420s 97356.941us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 98.420s 97356.941us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 98.420s 97356.941us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 5.280s 371.884us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.290s 43.435us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 98.420s 97356.941us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 112.410s 2735.285us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 5.280s 371.884us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
kmac_stress_all_with_rand_reset 73.450s 3368.424us 1 1 100.00