Simulation Results: kmac/unmasked

 
23/04/2026 19:40:15 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.18 %
  • code
  • 88.53 %
  • assert
  • 95.95 %
  • func
  • 92.06 %
  • line
  • 97.20 %
  • branch
  • 94.79 %
  • cond
  • 91.35 %
  • toggle
  • 99.83 %
  • FSM
  • 59.50 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 37.150s 994.936us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.040s 44.125us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.980s 51.322us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 6.780s 954.489us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 3.920s 1371.581us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 2.110s 48.308us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.980s 51.322us 1 1 100.00
kmac_csr_aliasing 3.920s 1371.581us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.850s 24.865us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.410s 37.663us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 804.720s 21818.509us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 408.380s 15085.624us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 1743.990s 94015.217us 1 1 100.00
kmac_test_vectors_sha3_256 26.690s 1634.124us 1 1 100.00
kmac_test_vectors_sha3_384 18.480s 1125.407us 1 1 100.00
kmac_test_vectors_sha3_512 13.030s 1822.061us 1 1 100.00
kmac_test_vectors_shake_128 153.100s 19514.533us 1 1 100.00
kmac_test_vectors_shake_256 293.970s 46545.838us 1 1 100.00
kmac_test_vectors_kmac 1.820s 114.783us 1 1 100.00
kmac_test_vectors_kmac_xof 3.090s 1462.955us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 206.330s 33099.884us 1 1 100.00
app 1 1 100.00
kmac_app 86.210s 24890.090us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 19.940s 922.907us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 95.470s 6100.874us 1 1 100.00
error 1 1 100.00
kmac_error 236.430s 23032.342us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 2.390s 447.304us 1 1 100.00
sideload_invalid 1 1 100.00
kmac_sideload_invalid 3.200s 330.098us 1 1 100.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 7.910s 319.719us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 18.670s 540.834us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 4.860s 3103.807us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.250s 40.963us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 845.970s 483384.202us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.950s 24.914us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.940s 26.099us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.530s 59.769us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.530s 59.769us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.040s 44.125us 1 1 100.00
kmac_csr_rw 0.980s 51.322us 1 1 100.00
kmac_csr_aliasing 3.920s 1371.581us 1 1 100.00
kmac_same_csr_outstanding 2.730s 189.050us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.040s 44.125us 1 1 100.00
kmac_csr_rw 0.980s 51.322us 1 1 100.00
kmac_csr_aliasing 3.920s 1371.581us 1 1 100.00
kmac_same_csr_outstanding 2.730s 189.050us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 2.010s 140.866us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 2.010s 140.866us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 2.010s 140.866us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 2.010s 140.866us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.430s 342.402us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 36.970s 4018.195us 1 1 100.00
kmac_tl_intg_err 2.820s 152.257us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.820s 152.257us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.250s 40.963us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 37.150s 994.936us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 206.330s 33099.884us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 2.010s 140.866us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 36.970s 4018.195us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 36.970s 4018.195us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 36.970s 4018.195us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 37.150s 994.936us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.250s 40.963us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 36.970s 4018.195us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 48.950s 3007.939us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 37.150s 994.936us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 43.720s 1951.690us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 44032852617403174154540291255054815885426431104171430255749769214273766769946 251
UVM_INFO @ 1951689711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---