Simulation Results: lc_ctrl/volatile_unlock_disabled

 
23/04/2026 19:40:15 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.58 %
  • code
  • 85.75 %
  • assert
  • 95.99 %
  • func
  • 92.99 %
  • line
  • 97.63 %
  • branch
  • 95.91 %
  • cond
  • 79.84 %
  • toggle
  • 89.90 %
  • FSM
  • 65.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.650s 41.434us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.340s 20.457us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.990s 49.268us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.630s 111.464us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.290s 78.689us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.190s 52.353us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.990s 49.268us 1 1 100.00
lc_ctrl_csr_aliasing 1.290s 78.689us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.210s 94.157us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.590s 325.001us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.980s 33.315us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.650s 104.381us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 10.790s 715.633us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.120s 243.549us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 10.790s 715.633us 1 1 100.00
lc_ctrl_prog_failure 1.650s 104.381us 1 1 100.00
lc_ctrl_errors 6.120s 243.549us 1 1 100.00
lc_ctrl_security_escalation 3.690s 920.046us 1 1 100.00
lc_ctrl_jtag_state_failure 51.050s 2655.392us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.640s 327.329us 1 1 100.00
lc_ctrl_jtag_errors 19.450s 988.189us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.220s 327.957us 1 1 100.00
lc_ctrl_jtag_state_post_trans 24.870s 2262.543us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.640s 327.329us 1 1 100.00
lc_ctrl_jtag_errors 19.450s 988.189us 1 1 100.00
lc_ctrl_jtag_access 2.430s 965.791us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 22.640s 5258.398us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.650s 982.206us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.930s 152.879us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.160s 3715.305us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.550s 990.049us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.150s 49.175us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.010s 1035.176us 1 1 100.00
lc_ctrl_jtag_alert_test 1.120s 60.007us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 9.270s 3715.774us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.790s 26.592us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 456.420s 91929.352us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.160s 180.947us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.390s 294.825us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.390s 294.825us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.340s 20.457us 1 1 100.00
lc_ctrl_csr_rw 0.990s 49.268us 1 1 100.00
lc_ctrl_csr_aliasing 1.290s 78.689us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.130s 101.479us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.340s 20.457us 1 1 100.00
lc_ctrl_csr_rw 0.990s 49.268us 1 1 100.00
lc_ctrl_csr_aliasing 1.290s 78.689us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.130s 101.479us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.240s 2150.113us 1 1 100.00
lc_ctrl_tl_intg_err 3.160s 671.939us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.160s 671.939us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.590s 325.001us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 10.790s 715.633us 1 1 100.00
lc_ctrl_sec_cm 7.240s 2150.113us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 10.790s 715.633us 1 1 100.00
lc_ctrl_sec_cm 7.240s 2150.113us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 10.790s 715.633us 1 1 100.00
lc_ctrl_sec_cm 7.240s 2150.113us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 10.790s 715.633us 1 1 100.00
lc_ctrl_sec_cm 7.240s 2150.113us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 10.790s 715.633us 1 1 100.00
lc_ctrl_sec_cm 7.240s 2150.113us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 10.790s 715.633us 1 1 100.00
lc_ctrl_sec_cm 7.240s 2150.113us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 10.790s 715.633us 1 1 100.00
lc_ctrl_sec_cm 7.240s 2150.113us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 10.790s 715.633us 1 1 100.00
lc_ctrl_sec_cm 7.240s 2150.113us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.690s 920.046us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.210s 94.157us 1 1 100.00
lc_ctrl_jtag_state_post_trans 24.870s 2262.543us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.310s 1445.110us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.310s 1445.110us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.860s 639.444us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.180s 374.707us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.180s 374.707us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 16.990s 1028.604us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 38903089046875810160232608036361059788270509354593277211591888382864018968523 430
UVM_INFO @ 1028603546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---