Simulation Results: lc_ctrl/volatile_unlock_enabled

 
23/04/2026 19:40:15 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.92 %
  • code
  • 86.24 %
  • assert
  • 95.99 %
  • func
  • 93.53 %
  • line
  • 97.71 %
  • branch
  • 96.01 %
  • cond
  • 79.23 %
  • toggle
  • 90.98 %
  • FSM
  • 67.27 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.050s 40.242us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.950s 30.617us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.950s 13.705us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.520s 92.309us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.960s 87.364us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.040s 273.974us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.950s 13.705us 1 1 100.00
lc_ctrl_csr_aliasing 0.960s 87.364us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.250s 91.604us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 10.480s 494.775us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.860s 14.012us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.350s 50.532us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.920s 182.355us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.930s 329.370us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.920s 182.355us 1 1 100.00
lc_ctrl_prog_failure 2.350s 50.532us 1 1 100.00
lc_ctrl_errors 7.930s 329.370us 1 1 100.00
lc_ctrl_security_escalation 6.740s 1859.378us 1 1 100.00
lc_ctrl_jtag_state_failure 48.010s 2291.608us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.410s 4516.017us 1 1 100.00
lc_ctrl_jtag_errors 14.960s 1474.616us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.120s 95.071us 1 1 100.00
lc_ctrl_jtag_state_post_trans 13.100s 720.592us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.410s 4516.017us 1 1 100.00
lc_ctrl_jtag_errors 14.960s 1474.616us 1 1 100.00
lc_ctrl_jtag_access 1.750s 211.981us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 24.800s 4981.286us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.780s 531.664us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.600s 152.135us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 12.610s 753.604us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 10.690s 637.652us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.920s 27.391us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.090s 62.978us 1 1 100.00
lc_ctrl_jtag_alert_test 0.830s 73.421us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 14.150s 4256.865us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.010s 12.967us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 143.920s 129542.760us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.110s 22.195us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.160s 78.838us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.160s 78.838us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.950s 30.617us 1 1 100.00
lc_ctrl_csr_rw 0.950s 13.705us 1 1 100.00
lc_ctrl_csr_aliasing 0.960s 87.364us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.330s 24.505us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.950s 30.617us 1 1 100.00
lc_ctrl_csr_rw 0.950s 13.705us 1 1 100.00
lc_ctrl_csr_aliasing 0.960s 87.364us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.330s 24.505us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.650s 122.234us 1 1 100.00
lc_ctrl_tl_intg_err 1.750s 79.882us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.750s 79.882us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 10.480s 494.775us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.920s 182.355us 1 1 100.00
lc_ctrl_sec_cm 6.650s 122.234us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.920s 182.355us 1 1 100.00
lc_ctrl_sec_cm 6.650s 122.234us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.920s 182.355us 1 1 100.00
lc_ctrl_sec_cm 6.650s 122.234us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.920s 182.355us 1 1 100.00
lc_ctrl_sec_cm 6.650s 122.234us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.920s 182.355us 1 1 100.00
lc_ctrl_sec_cm 6.650s 122.234us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.920s 182.355us 1 1 100.00
lc_ctrl_sec_cm 6.650s 122.234us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.920s 182.355us 1 1 100.00
lc_ctrl_sec_cm 6.650s 122.234us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.920s 182.355us 1 1 100.00
lc_ctrl_sec_cm 6.650s 122.234us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.740s 1859.378us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.250s 91.604us 1 1 100.00
lc_ctrl_jtag_state_post_trans 13.100s 720.592us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.510s 993.138us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.510s 993.138us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.650s 2200.082us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.150s 2151.638us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.150s 2151.638us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 47.540s 4570.565us 1 1 100.00