Simulation Results: otbn

 
23/04/2026 19:40:15 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.05 %
  • code
  • 94.59 %
  • assert
  • 89.67 %
  • func
  • 97.88 %
  • block
  • 99.37 %
  • line
  • 99.56 %
  • branch
  • 92.10 %
  • toggle
  • 91.84 %
  • FSM
  • 94.87 %
Validation stages
V1
100.00%
V2
78.57%
V2S
84.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 11.000s 118.740us 1 1 100.00
single_binary 1 1 100.00
otbn_single 10.000s 34.275us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 4.000s 77.356us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 3.000s 45.708us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 6.000s 29.400us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 3.000s 30.532us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 8.000s 43.413us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 3.000s 45.708us 1 1 100.00
otbn_csr_aliasing 3.000s 30.532us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 88.000s 1035.643us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 50.000s 5132.980us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 25.000s 100.383us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 55.000s 227.658us 1 1 100.00
back_to_back 0 1 0.00
otbn_multi 6.000s 29.169us 0 1 0.00
stress_all 0 1 0.00
otbn_stress_all 36.213s 0.000us 0 1 0.00
lc_escalation 1 1 100.00
otbn_escalate 8.000s 20.804us 1 1 100.00
zero_state_err_urnd 0 1 0.00
otbn_zero_state_err_urnd 6.000s 15.407us 0 1 0.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 6.000s 50.570us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 4.000s 63.289us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 4.000s 35.969us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 8.000s 1197.589us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 8.000s 1197.589us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 4.000s 77.356us 1 1 100.00
otbn_csr_rw 3.000s 45.708us 1 1 100.00
otbn_csr_aliasing 3.000s 30.532us 1 1 100.00
otbn_same_csr_outstanding 3.000s 86.063us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 4.000s 77.356us 1 1 100.00
otbn_csr_rw 3.000s 45.708us 1 1 100.00
otbn_csr_aliasing 3.000s 30.532us 1 1 100.00
otbn_same_csr_outstanding 3.000s 86.063us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 8.000s 16.301us 1 1 100.00
otbn_dmem_err 9.000s 21.756us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 6.000s 191.739us 1 1 100.00
otbn_controller_ispr_rdata_err 9.000s 212.038us 1 1 100.00
otbn_mac_bignum_acc_err 7.000s 98.278us 1 1 100.00
otbn_urnd_err 4.000s 26.101us 0 1 0.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 6.000s 22.069us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 6.000s 17.648us 1 1 100.00
otbn_non_sec_partial_wipe 0 1 0.00
otbn_partial_wipe 4.000s 24.516us 0 1 0.00
tl_intg_err 2 2 100.00
otbn_sec_cm 98.000s 1004.991us 1 1 100.00
otbn_tl_intg_err 15.000s 1803.652us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 42.000s 411.087us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 98.000s 1004.991us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 98.000s 1004.991us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 11.000s 118.740us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 9.000s 21.756us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 8.000s 16.301us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 15.000s 1803.652us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 8.000s 20.804us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 8.000s 16.301us 1 1 100.00
otbn_dmem_err 9.000s 21.756us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 15.407us 0 1 0.00
otbn_illegal_mem_acc 6.000s 22.069us 1 1 100.00
otbn_sec_cm 98.000s 1004.991us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 98.000s 1004.991us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 10.000s 34.275us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 8.000s 16.301us 1 1 100.00
otbn_dmem_err 9.000s 21.756us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 15.407us 0 1 0.00
otbn_illegal_mem_acc 6.000s 22.069us 1 1 100.00
otbn_sec_cm 98.000s 1004.991us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 98.000s 1004.991us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 8.000s 20.804us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 8.000s 16.301us 1 1 100.00
otbn_dmem_err 9.000s 21.756us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 15.407us 0 1 0.00
otbn_illegal_mem_acc 6.000s 22.069us 1 1 100.00
otbn_sec_cm 98.000s 1004.991us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 98.000s 1004.991us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 10.000s 34.275us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 8.000s 212.614us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 7.000s 81.913us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 50.000s 130.269us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 50.000s 130.269us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 7.000s 35.488us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 98.000s 1004.991us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 98.000s 1004.991us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 7.000s 848.794us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 98.000s 1004.991us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 98.000s 1004.991us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 9.000s 28.492us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 9.000s 28.492us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 16.000s 58.837us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 10.000s 34.275us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 10.000s 34.275us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 10.000s 34.275us 1 1 100.00
sec_cm_write_mem_integrity 0 1 0.00
otbn_multi 6.000s 29.169us 0 1 0.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 10.000s 34.275us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 10.000s 34.275us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 7.000s 13.138us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 10.000s 34.275us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 98.000s 1004.991us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 98.000s 572.343us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 8.000s 27.933us 1 1 100.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,152): Assertion NoModelErrs has failed
otbn_multi 55678520551822741024573668620490489396016074156391016777411844852288048070093 152
UVM_ERROR @ 29169286 ps: (otbn_model_if.sv:152) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 29169286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']
otbn_stress_all 56542433937433998127404100774650554977468480885800657655222374835692824603545 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 48791643088892629146977529802795002048779815622117607339510451545925347434692 196
UVM_INFO @ 572343282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
otbn_zero_state_err_urnd 77068270132684356020288382089604261835503380802736928616517175421839089740344 105
UVM_INFO @ 15406570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.edn_urnd_ack cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
otbn_urnd_err 70396531153909922306395405459687791190893054009681723507797526387771749501557 106
UVM_INFO @ 26100640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status
otbn_partial_wipe 14329257715724217383250514029556183025531251601842943433546304435572907398443 114
UVM_INFO @ 24516240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---