Simulation Results: otp_ctrl

 
23/04/2026 19:40:15 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.71 %
  • code
  • 69.34 %
  • assert
  • 92.99 %
  • func
  • 49.79 %
  • line
  • 87.05 %
  • branch
  • 83.25 %
  • cond
  • 85.18 %
  • toggle
  • 59.96 %
  • FSM
  • 31.26 %
Validation stages
V1
100.00%
V2
55.00%
V2S
66.67%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.860s 217.656us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 6.190s 505.321us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.690s 213.022us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.820s 101.598us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 7.120s 886.501us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 7.350s 522.159us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.270s 1978.788us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.820s 101.598us 1 1 100.00
otp_ctrl_csr_aliasing 7.350s 522.159us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.460s 92.269us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.300s 45.508us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 118.980s 13046.426us 0 1 0.00
init_fail 0 1 0.00
otp_ctrl_init_fail 3.050s 955.655us 0 1 0.00
partition_check 1 2 50.00
otp_ctrl_background_chks 6.170s 978.180us 0 1 0.00
otp_ctrl_check_fail 3.370s 584.593us 1 1 100.00
regwen_during_otp_init 0 1 0.00
otp_ctrl_regwen 4.660s 421.030us 0 1 0.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 12.940s 1980.339us 1 1 100.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 15.300s 1393.885us 0 1 0.00
lc_interactions 1 2 50.00
otp_ctrl_parallel_lc_req 15.610s 1093.944us 0 1 0.00
otp_ctrl_parallel_lc_esc 17.990s 4039.523us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 13.530s 964.858us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 12.600s 2360.288us 0 1 0.00
test_access 0 1 0.00
otp_ctrl_test_access 7.750s 524.653us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 23.660s 1475.884us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.570s 48.223us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.760s 200.014us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 2.770s 156.283us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 2.770s 156.283us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.690s 213.022us 1 1 100.00
otp_ctrl_csr_rw 1.820s 101.598us 1 1 100.00
otp_ctrl_csr_aliasing 7.350s 522.159us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.670s 77.121us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.690s 213.022us 1 1 100.00
otp_ctrl_csr_rw 1.820s 101.598us 1 1 100.00
otp_ctrl_csr_aliasing 7.350s 522.159us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.670s 77.121us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 245.430s 16001.154us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 245.430s 16001.154us 1 1 100.00
otp_ctrl_tl_intg_err 11.630s 851.247us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 245.430s 16001.154us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 245.430s 16001.154us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 11.630s 851.247us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 6.190s 505.321us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 6.190s 505.321us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 245.430s 16001.154us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 245.430s 16001.154us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 245.430s 16001.154us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 245.430s 16001.154us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 245.430s 16001.154us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 245.430s 16001.154us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 245.430s 16001.154us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 245.430s 16001.154us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 245.430s 16001.154us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 245.430s 16001.154us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 245.430s 16001.154us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 245.430s 16001.154us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 245.430s 16001.154us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 245.430s 16001.154us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 245.430s 16001.154us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 17.990s 4039.523us 1 1 100.00
otp_ctrl_sec_cm 245.430s 16001.154us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 17.990s 4039.523us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 17.990s 4039.523us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 17.990s 4039.523us 1 1 100.00
otp_ctrl_macro_errs 12.600s 2360.288us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 17.990s 4039.523us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 17.990s 4039.523us 1 1 100.00
otp_ctrl_sec_cm 245.430s 16001.154us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 17.990s 4039.523us 1 1 100.00
otp_ctrl_sec_cm 245.430s 16001.154us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 17.990s 4039.523us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 17.990s 4039.523us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 17.990s 4039.523us 1 1 100.00
otp_ctrl_macro_errs 12.600s 2360.288us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 17.990s 4039.523us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 17.990s 4039.523us 1 1 100.00
otp_ctrl_sec_cm 245.430s 16001.154us 1 1 100.00
sec_cm_part_data_reg_integrity 0 1 0.00
otp_ctrl_init_fail 3.050s 955.655us 0 1 0.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 3.370s 584.593us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 12.940s 1980.339us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 12.940s 1980.339us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 12.940s 1980.339us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 12.940s 1980.339us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 12.940s 1980.339us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 6.190s 505.321us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 12.940s 1980.339us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 6.190s 505.321us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 245.430s 16001.154us 1 1 100.00
sec_cm_direct_access_config_regwen 0 1 0.00
otp_ctrl_regwen 4.660s 421.030us 0 1 0.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 6.190s 505.321us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 6.190s 505.321us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 12.600s 2360.288us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 124.880s 59052.150us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 2.170s 67.302us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch
otp_ctrl_partition_walk 22026958567349846328076929706527082850046551656837988033492680247787401779741 112725
UVM_INFO @ 13046426017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch
otp_ctrl_low_freq_read 97776517543236804328392211420303314108167926914628887071865602400381665256779 89
UVM_INFO @ 59052149701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: *
otp_ctrl_init_fail 49217780142660424676149844619562273336285565115804429374827816606923188812854 635
UVM_INFO @ 955654843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_regwen 1713718325559067488234297379053320149486396792353671221252153798727116411558 5078
UVM_INFO @ 421030000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_*
otp_ctrl_background_chks 36807552579374623877415841214391666099693946257075889122869190068599207527767 4566
UVM_INFO @ 978180167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 97978668515100070685639760850058855335150329781719693251224497371060325863346 21605
UVM_INFO @ 1475884362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:958) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask *
otp_ctrl_parallel_lc_req 33494393906796338874917569772029423245450262812507887014081840662285317775965 17061
UVM_INFO @ 1093944049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_macro_errs 77629925752946437914359285303924835527615718865007072361000544358448103587241 298
UVM_INFO @ 2360288161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state
otp_ctrl_parallel_key_req 111217367533942944520659795829756831587920322916287150743682669764100983354988 14073
UVM_INFO @ 1393884954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:671) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr
otp_ctrl_test_access 51611463067101683400346057741412829742283393101523219451153446685005579240091 6114
UVM_INFO @ 524652688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:2213) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 7413531771220563232868275267223300354447125968410249324718165862927822569852 395
UVM_INFO @ 67302391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---