Simulation Results: rom_ctrl/32kb

 
23/04/2026 19:40:15 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.66 %
  • code
  • 99.05 %
  • assert
  • 96.80 %
  • func
  • 97.14 %
  • line
  • 99.59 %
  • branch
  • 98.91 %
  • cond
  • 97.18 %
  • toggle
  • 99.57 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.700s 669.351us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.710s 137.303us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.580s 129.242us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.430s 129.507us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.280s 213.382us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.200s 631.456us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.580s 129.242us 1 1 100.00
rom_ctrl_csr_aliasing 3.280s 213.382us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.300s 129.147us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.110s 372.489us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 3.740s 501.163us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 8.930s 590.377us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.700s 303.436us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.180s 180.721us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.380s 698.060us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.380s 698.060us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.710s 137.303us 1 1 100.00
rom_ctrl_csr_rw 3.580s 129.242us 1 1 100.00
rom_ctrl_csr_aliasing 3.280s 213.382us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.970s 1751.306us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.710s 137.303us 1 1 100.00
rom_ctrl_csr_rw 3.580s 129.242us 1 1 100.00
rom_ctrl_csr_aliasing 3.280s 213.382us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.970s 1751.306us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 2495.508us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 16.610s 590.036us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 194.550s 1617.923us 1 1 100.00
rom_ctrl_tl_intg_err 42.680s 1039.966us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 194.550s 1617.923us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 194.550s 1617.923us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 2495.508us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 2495.508us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 2495.508us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 2495.508us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 2495.508us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 194.550s 1617.923us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 194.550s 1617.923us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.700s 669.351us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.700s 669.351us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.700s 669.351us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 42.680s 1039.966us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 2495.508us 1 1 100.00
rom_ctrl_kmac_err_chk 7.700s 303.436us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 2495.508us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 2495.508us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 2495.508us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 16.610s 590.036us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 194.550s 1617.923us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 25.830s 2591.810us 1 1 100.00