Simulation Results: rom_ctrl/64kb

 
23/04/2026 19:40:15 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.37 %
  • code
  • 97.95 %
  • assert
  • 96.80 %
  • func
  • 97.37 %
  • line
  • 99.32 %
  • branch
  • 98.91 %
  • cond
  • 98.22 %
  • toggle
  • 99.95 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.540s 221.469us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 9.750s 739.224us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.260s 727.106us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.050s 221.194us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.500s 824.664us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.830s 305.785us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.260s 727.106us 1 1 100.00
rom_ctrl_csr_aliasing 5.500s 824.664us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 7.820s 1412.190us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.940s 487.264us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 8.140s 1116.862us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 19.960s 1679.195us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 12.040s 1422.683us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.590s 205.592us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 11.320s 544.907us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 11.320s 544.907us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.750s 739.224us 1 1 100.00
rom_ctrl_csr_rw 6.260s 727.106us 1 1 100.00
rom_ctrl_csr_aliasing 5.500s 824.664us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.150s 729.871us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.750s 739.224us 1 1 100.00
rom_ctrl_csr_rw 6.260s 727.106us 1 1 100.00
rom_ctrl_csr_aliasing 5.500s 824.664us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.150s 729.871us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 132.440s 5891.599us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.400s 2064.063us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 443.080s 736.137us 1 1 100.00
rom_ctrl_tl_intg_err 51.700s 302.369us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 443.080s 736.137us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 443.080s 736.137us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 132.440s 5891.599us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 132.440s 5891.599us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 132.440s 5891.599us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 132.440s 5891.599us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 132.440s 5891.599us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 443.080s 736.137us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 443.080s 736.137us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.540s 221.469us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.540s 221.469us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.540s 221.469us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 51.700s 302.369us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 132.440s 5891.599us 1 1 100.00
rom_ctrl_kmac_err_chk 12.040s 1422.683us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 132.440s 5891.599us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 132.440s 5891.599us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 132.440s 5891.599us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.400s 2064.063us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 443.080s 736.137us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 60.360s 1633.167us 1 1 100.00