Simulation Results: rstmgr

 
23/04/2026 19:40:15 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.85 %
  • code
  • 99.31 %
  • assert
  • 97.25 %
  • func
  • 96.99 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.64 %
  • toggle
  • 99.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.460s 66.593us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.160s 94.427us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.810s 38.742us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.420s 115.906us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.060s 42.047us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.000s 65.394us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.810s 38.742us 1 1 100.00
rstmgr_csr_aliasing 1.060s 42.047us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.030s 90.280us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.210s 41.088us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.900s 42.071us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.610s 617.142us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.610s 617.142us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.610s 617.142us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.610s 617.142us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 26.590s 4363.442us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.950s 42.274us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.220s 51.291us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.220s 51.291us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.160s 94.427us 1 1 100.00
rstmgr_csr_rw 0.810s 38.742us 1 1 100.00
rstmgr_csr_aliasing 1.060s 42.047us 1 1 100.00
rstmgr_same_csr_outstanding 1.490s 72.358us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.160s 94.427us 1 1 100.00
rstmgr_csr_rw 0.810s 38.742us 1 1 100.00
rstmgr_csr_aliasing 1.060s 42.047us 1 1 100.00
rstmgr_same_csr_outstanding 1.490s 72.358us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 30.070s 6867.553us 1 1 100.00
rstmgr_tl_intg_err 3.950s 632.848us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 30.070s 6867.553us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 30.070s 6867.553us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 3.950s 632.848us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.230s 54.492us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.940s 452.787us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.030s 291.801us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 30.070s 6867.553us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.810s 38.742us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.810s 38.742us 1 1 100.00