Simulation Results

Simulation Results: rv_dm/use_dmi_interface

23/04/2026 19:40:15 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
73.85 %

code
73.61 %

assert
96.16 %

func
51.78 %

line
90.22 %

branch
75.00 %

cond
76.32 %

toggle
70.27 %

FSM
56.25 %

Validation stages

V1		96.30%
V2		69.57%
V2S		100.00%
V3		0.00%
unmapped		0.00%

26/27 passed

96.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	2.200s	2216.718us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	0.990s	320.433us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	0.880s	144.967us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	2.760s	5381.354us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	4.700s	2200.089us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	4.350s	3422.443us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	3.680s	2876.522us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	2.150s	5552.048us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	33.610s	34300.995us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	0.940s	274.378us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	1.470s	645.382us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	0.850s	252.095us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	1.010s	156.022us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	0.950s	651.307us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	0.880s	164.366us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	0.670s	93.117us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	1.480s	1542.882us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	0.940s	274.378us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	0.920s	209.061us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	1.050s	358.991us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	0.850s	252.095us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	0.790s	193.021us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	2.070s	283.050us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	1.280s	133.860us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	19.270s	767.215us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	40.920s	1480.015us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	1.540s	199.524us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	40.920s	1480.015us	1	1	100.00
	rv_dm_csr_rw	1.280s	133.860us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	0.660s	59.328us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	0.760s	154.506us	1	1	100.00

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	2.200s	2216.718us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	0.730s	154.165us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	0.680s	149.319us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	0.960s	650.838us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	1.810s	916.684us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	487.710s	300000.000us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	545.540s	300000.000us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	165.940s	300000.000us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	82.090s	300000.000us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	0.950s	124.565us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	2.450s	2050.419us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	1.160s	269.821us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	1.060s	253.384us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	6.530s	6163.655us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	62.680s	13093.263us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	0.730s	98.373us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	0.870s	179.330us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	0.740s	57.000us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	3.090s	358.029us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	3.090s	358.029us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	40.920s	1480.015us	1	1	100.00
	rv_dm_csr_hw_reset	2.070s	283.050us	1	1	100.00
	rv_dm_csr_rw	1.280s	133.860us	1	1	100.00
	rv_dm_same_csr_outstanding	2.990s	262.942us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	40.920s	1480.015us	1	1	100.00
	rv_dm_csr_hw_reset	2.070s	283.050us	1	1	100.00
	rv_dm_csr_rw	1.280s	133.860us	1	1	100.00
	rv_dm_same_csr_outstanding	2.990s	262.942us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	2.270s	589.799us	1	1	100.00
	rv_dm_tl_intg_err	9.180s	2358.236us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	9.180s	2358.236us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	2.450s	2050.419us	1	1	100.00
	rv_dm_debug_disabled	0.830s	45.013us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	2.450s	2050.419us	1	1	100.00
	rv_dm_debug_disabled	0.830s	45.013us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	2.200s	2216.718us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	0.970s	422.615us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	1.080s	74.196us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	1.080s	74.196us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	0.970s	422.615us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	9.380s	871.834us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	281.940s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
	rv_dm_sba_tl_access	61773171938702019106264391841620013684690775525033329780824661747355908314398	86	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	32353826993251357488622467935535181764358326823078423656289580986495200898536	86	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	45437522164715523720874672736704269240184861966093514702790472113763115099966	86	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	60127687116388455608948791650463874535875792840682888665561137439237992434429	86	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_scanmode	11438140424721415780406709339766971559807988709227981396972337626489258813629	77	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 'b (* [] vs [*])
	rv_dm_mem_tl_access_resuming	98580386247642892667371426922485140520978883772480126668711844976630303348673	77	UVM_INFO @ 156022152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	11924845357560040268002656705724962577539803627983111701204659887397298426381	78	UVM_INFO @ 179329939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [] vs [*])
	rv_dm_hart_unavail	31348983232867556294197361681986789716118593207896062933559084806553748301016	77	UVM_INFO @ 253384123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	66677753318307291930411638359608256056621505910713525856131140733443531190447	93	UVM_INFO @ 871834346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])
	rv_dm_jtag_dmi_debug_disabled	54997495872734580806700257630859953897091396721580172992936203139793713205698	77	UVM_INFO @ 124564631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---