Simulation Results: rv_timer

 
23/04/2026 19:40:15 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.98 %
  • code
  • 99.94 %
  • assert
  • 96.82 %
  • func
  • 91.18 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 99.74 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 2.150s 91.811us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.560s 49.334us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.620s 14.178us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.360s 148.914us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.100s 32.143us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.690s 15.392us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.620s 14.178us 1 1 100.00
rv_timer_csr_aliasing 1.100s 32.143us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.880s 136.155us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 0.940s 3116.942us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 270.880s 370619.325us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 270.880s 370619.325us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.360s 956.591us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.670s 44.482us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.630s 13.117us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.420s 443.290us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.420s 443.290us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.560s 49.334us 1 1 100.00
rv_timer_csr_rw 0.620s 14.178us 1 1 100.00
rv_timer_csr_aliasing 1.100s 32.143us 1 1 100.00
rv_timer_same_csr_outstanding 0.720s 81.924us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.560s 49.334us 1 1 100.00
rv_timer_csr_rw 0.620s 14.178us 1 1 100.00
rv_timer_csr_aliasing 1.100s 32.143us 1 1 100.00
rv_timer_same_csr_outstanding 0.720s 81.924us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.750s 69.307us 1 1 100.00
rv_timer_tl_intg_err 1.110s 320.071us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.110s 320.071us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.880s 127.343us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.890s 43.791us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 6.750s 920.407us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 11238154377519361376066031753374816014008327991717702321312274191854296788270 76
UVM_INFO @ 127342865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 78152993413472132090025166676221264204027565268872700063595694103606978445538 76
UVM_INFO @ 136154883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:346) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*])
rv_timer_max 93497716785593873611152223584276312102353380618878491542582913310777830108098 75
UVM_INFO @ 43790953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---