Simulation Results: spi_host

 
23/04/2026 19:40:15 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.42 %
  • code
  • 94.90 %
  • assert
  • 94.13 %
  • func
  • 88.24 %
  • block
  • 96.78 %
  • line
  • 98.54 %
  • branch
  • 93.05 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 51.000s 3207.506us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 68.792us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 16.260us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 424.153us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 37.776us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 50.356us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 16.260us 1 1 100.00
spi_host_csr_aliasing 2.000s 37.776us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 31.384us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 23.178us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 66.695us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 31.410us 1 1 100.00
spi_host_error_cmd 1.000s 51.170us 1 1 100.00
spi_host_event 102.000s 19397.831us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 3.000s 217.041us 1 1 100.00
speed 1 1 100.00
spi_host_speed 3.000s 217.041us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 3.000s 217.041us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 8.000s 394.540us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 356.082us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 3.000s 217.041us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 3.000s 217.041us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 51.000s 3207.506us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 51.000s 3207.506us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 2.000s 202.282us 1 1 100.00
spien 1 1 100.00
spi_host_spien 5.000s 1620.205us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 21.000s 2780.875us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 753.303us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 31.410us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 24.477us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 45.642us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 3.000s 177.272us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 3.000s 177.272us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 68.792us 1 1 100.00
spi_host_csr_rw 1.000s 16.260us 1 1 100.00
spi_host_csr_aliasing 2.000s 37.776us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 75.843us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 68.792us 1 1 100.00
spi_host_csr_rw 1.000s 16.260us 1 1 100.00
spi_host_csr_aliasing 2.000s 37.776us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 75.843us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 1.000s 181.245us 1 1 100.00
spi_host_sec_cm 1.000s 160.497us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 181.245us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
spi_host_upper_range_clkdiv 690.000s 122266.044us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=*
spi_host_upper_range_clkdiv 67890143982325123852947971086299162932810845942566084543885137212852645505935 174
UVM_INFO @ 122266044082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---