Simulation Results: sram_ctrl/main

 
23/04/2026 19:40:15 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.19 %
  • code
  • 95.78 %
  • assert
  • 96.19 %
  • func
  • 93.60 %
  • block
  • 94.73 %
  • line
  • 95.33 %
  • branch
  • 91.73 %
  • toggle
  • 96.04 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 1426.481us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 78.153us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.959us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 176.697us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 19.688us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 691.314us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 18.959us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 19.688us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 90.000s 10521.995us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 46.000s 2404.817us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 33.000s 26699.561us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 96.000s 14190.970us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 140.000s 10019.006us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 40.000s 10140.647us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 22.000s 5951.506us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 32.000s 6554.757us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 1473.732us 1 1 100.00
sram_ctrl_partial_access_b2b 233.000s 18092.864us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 4.000s 1391.016us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.000s 1356.572us 1 1 100.00
sram_ctrl_throughput_w_readback 4.000s 682.627us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 14.000s 4589.291us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.000s 697.334us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 484.000s 102570.434us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 14.047us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 42.054us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 42.054us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 78.153us 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.959us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 19.688us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 15.667us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 78.153us 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.959us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 19.688us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 15.667us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 25.000s 15229.140us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 1907.782us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 137.998us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 1907.782us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 137.998us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 14.000s 4589.291us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 14.000s 4589.291us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.959us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 32.000s 6554.757us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 32.000s 6554.757us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 32.000s 6554.757us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 22.000s 5951.506us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 704.954us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 25.000s 15229.140us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 6.000s 675.322us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 1426.481us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 1426.481us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 32.000s 6554.757us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 1907.782us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 22.000s 5951.506us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 1907.782us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1907.782us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 1426.481us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1907.782us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 8.000s 369.730us 1 1 100.00