Simulation Results: sram_ctrl/ret

 
23/04/2026 19:40:15 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.35 %
  • code
  • 83.36 %
  • assert
  • 96.29 %
  • func
  • 94.40 %
  • block
  • 93.80 %
  • line
  • 94.97 %
  • branch
  • 89.51 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 45.979us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 21.832us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 46.896us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 123.902us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 38.889us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 65.434us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 46.896us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 38.889us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 5.000s 625.605us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 5.000s 1275.009us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 5.000s 260.056us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 164.000s 7808.103us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 5.000s 111.933us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 23.000s 9114.061us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 2.000s 74.036us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 9.000s 2333.216us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 38.903us 1 1 100.00
sram_ctrl_partial_access_b2b 172.000s 91218.784us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 122.500us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 35.178us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 61.473us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 10.000s 168.388us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 179.514us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 25.000s 6062.486us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 17.239us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 437.683us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 437.683us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 21.832us 1 1 100.00
sram_ctrl_csr_rw 1.000s 46.896us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 38.889us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 93.875us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 21.832us 1 1 100.00
sram_ctrl_csr_rw 1.000s 46.896us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 38.889us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 93.875us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 491.453us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 893.119us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 153.054us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 893.119us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 153.054us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 10.000s 168.388us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 10.000s 168.388us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 46.896us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 9.000s 2333.216us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 2333.216us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 2333.216us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 2.000s 74.036us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 163.163us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 491.453us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 51.326us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 45.979us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 45.979us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 9.000s 2333.216us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 893.119us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 2.000s 74.036us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 893.119us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 893.119us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 45.979us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 893.119us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 64.000s 4103.285us 1 1 100.00