Simulation Results: uart

 
23/04/2026 19:40:15 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.38 %
  • code
  • 96.74 %
  • assert
  • 97.12 %
  • func
  • 50.28 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 97.78 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.320s 983.516us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.630s 18.379us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.620s 35.402us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.850s 448.931us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.840s 72.894us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.800s 221.081us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.620s 35.402us 1 1 100.00
uart_csr_aliasing 0.840s 72.894us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 50.830s 37043.476us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.320s 983.516us 1 1 100.00
uart_tx_rx 50.830s 37043.476us 1 1 100.00
parity_error 2 2 100.00
uart_intr 5.360s 38329.516us 1 1 100.00
uart_rx_parity_err 58.730s 105004.421us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 50.830s 37043.476us 1 1 100.00
uart_intr 5.360s 38329.516us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 52.610s 45184.293us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 61.670s 74889.473us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 17.350s 53163.128us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 5.360s 38329.516us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 5.360s 38329.516us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 5.360s 38329.516us 1 1 100.00
perf 1 1 100.00
uart_perf 161.620s 17707.471us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 2.860s 8541.361us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 2.860s 8541.361us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 1.060s 239.648us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 1.780s 3970.847us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.780s 2204.413us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 16.000s 5128.832us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 68.050s 76951.895us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 61.080s 104145.463us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.760s 34.014us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.660s 15.256us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.240s 85.283us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.240s 85.283us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.630s 18.379us 1 1 100.00
uart_csr_rw 0.620s 35.402us 1 1 100.00
uart_csr_aliasing 0.840s 72.894us 1 1 100.00
uart_same_csr_outstanding 0.830s 29.561us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.630s 18.379us 1 1 100.00
uart_csr_rw 0.620s 35.402us 1 1 100.00
uart_csr_aliasing 0.840s 72.894us 1 1 100.00
uart_same_csr_outstanding 0.830s 29.561us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.800s 145.718us 1 1 100.00
uart_tl_intg_err 1.160s 329.297us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.160s 329.297us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 27.840s 19068.743us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *
uart_noise_filter 40034528085947679161054608785065813487050953327033323960735113742504231114404 74
UVM_ERROR @ 181527342 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 181587948 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 253 [0xfd]) reg name: uart_reg_block.rdata
UVM_ERROR @ 184517238 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 184517238 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1