Simulation Results: aes/masked

 
27/04/2026 19:39:13 DVSim: v1.32.0 sha: 4c58639 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.56 %
  • code
  • 95.82 %
  • assert
  • 98.43 %
  • func
  • 65.43 %
  • block
  • 95.84 %
  • line
  • 97.52 %
  • branch
  • 89.64 %
  • toggle
  • 98.05 %
  • FSM
  • 98.06 %
Validation stages
V1
100.00%
V2
94.74%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 270.732us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 98.489us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 63.437us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 183.089us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 456.806us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 229.933us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 107.848us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 183.089us 1 1 100.00
aes_csr_aliasing 3.000s 229.933us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 98.489us 1 1 100.00
aes_config_error 4.000s 80.264us 1 1 100.00
aes_stress 4.000s 154.140us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 98.489us 1 1 100.00
aes_config_error 4.000s 80.264us 1 1 100.00
aes_stress 4.000s 154.140us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 154.140us 1 1 100.00
aes_b2b 6.000s 189.647us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 154.140us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 3.000s 98.489us 1 1 100.00
aes_config_error 4.000s 80.264us 1 1 100.00
aes_stress 4.000s 154.140us 1 1 100.00
aes_alert_reset 39.000s 10077.240us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 136.694us 1 1 100.00
aes_config_error 4.000s 80.264us 1 1 100.00
aes_alert_reset 39.000s 10077.240us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 5.000s 97.430us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 20.000s 2030.211us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 14.000s 871.595us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 39.000s 10077.240us 0 1 0.00
stress 1 1 100.00
aes_stress 4.000s 154.140us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 154.140us 1 1 100.00
aes_sideload 4.000s 216.059us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 74.391us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 3.000s 215.780us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 88.410us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 70.758us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 256.102us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 256.102us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 63.437us 1 1 100.00
aes_csr_rw 2.000s 183.089us 1 1 100.00
aes_csr_aliasing 3.000s 229.933us 1 1 100.00
aes_same_csr_outstanding 2.000s 179.582us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 63.437us 1 1 100.00
aes_csr_rw 2.000s 183.089us 1 1 100.00
aes_csr_aliasing 3.000s 229.933us 1 1 100.00
aes_same_csr_outstanding 2.000s 179.582us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 7.000s 169.261us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 53.000s 10014.955us 0 1 0.00
aes_control_fi 1.000s 67.867us 1 1 100.00
aes_cipher_fi 3.000s 56.049us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 233.869us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 233.869us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 233.869us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 233.869us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 111.409us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 6.000s 2709.648us 1 1 100.00
aes_tl_intg_err 2.000s 288.064us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 288.064us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 39.000s 10077.240us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 233.869us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 233.869us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 3.000s 98.489us 1 1 100.00
aes_stress 4.000s 154.140us 1 1 100.00
aes_alert_reset 39.000s 10077.240us 0 1 0.00
aes_core_fi 2.000s 141.402us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 3.000s 88.410us 1 1 100.00
aes_config_error 4.000s 80.264us 1 1 100.00
aes_stress 4.000s 154.140us 1 1 100.00
aes_core_fi 2.000s 141.402us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 233.869us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 95.352us 1 1 100.00
aes_stress 4.000s 154.140us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 154.140us 1 1 100.00
aes_sideload 4.000s 216.059us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 95.352us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 95.352us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 95.352us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 95.352us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 95.352us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 154.140us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 154.140us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 53.000s 10014.955us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 53.000s 10014.955us 0 1 0.00
aes_control_fi 1.000s 67.867us 1 1 100.00
aes_cipher_fi 3.000s 56.049us 1 1 100.00
aes_ctr_fi 2.000s 85.234us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 53.000s 10014.955us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 53.000s 10014.955us 0 1 0.00
aes_control_fi 1.000s 67.867us 1 1 100.00
aes_cipher_fi 3.000s 56.049us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 56.049us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 53.000s 10014.955us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 53.000s 10014.955us 0 1 0.00
aes_control_fi 1.000s 67.867us 1 1 100.00
aes_ctr_fi 2.000s 85.234us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 53.000s 10014.955us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 53.000s 10014.955us 0 1 0.00
aes_control_fi 1.000s 67.867us 1 1 100.00
aes_cipher_fi 3.000s 56.049us 1 1 100.00
aes_ctr_fi 2.000s 85.234us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 39.000s 10077.240us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 53.000s 10014.955us 0 1 0.00
aes_control_fi 1.000s 67.867us 1 1 100.00
aes_cipher_fi 3.000s 56.049us 1 1 100.00
aes_ctr_fi 2.000s 85.234us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 53.000s 10014.955us 0 1 0.00
aes_control_fi 1.000s 67.867us 1 1 100.00
aes_cipher_fi 3.000s 56.049us 1 1 100.00
aes_ctr_fi 2.000s 85.234us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 53.000s 10014.955us 0 1 0.00
aes_control_fi 1.000s 67.867us 1 1 100.00
aes_ctr_fi 2.000s 85.234us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 53.000s 10014.955us 0 1 0.00
aes_ghash_fi 2.000s 50.135us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 53.000s 10014.955us 0 1 0.00
aes_control_fi 1.000s 67.867us 1 1 100.00
aes_cipher_fi 3.000s 56.049us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 28.000s 2326.928us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred!
aes_alert_reset 68951404454184365849428195307102997958786829491000631545103717864747574497143 4430
UVM_INFO @ 10077240099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred!
aes_fi 35062531212547650164671314470502413657452498349713069081395403164606974469051 3418
UVM_INFO @ 10014954910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:306) virtual_sequencer [aes_reseed_vseq] Expected GCM phase GCM_AAD, got GCM_TEXT
aes_stress_all_with_rand_reset 7479336290199051301442781737242042478181555324049937267767230192603736051434 681
UVM_INFO @ 2326928402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---