Simulation Results: aes/unmasked

 
27/04/2026 19:39:13 DVSim: v1.32.0 sha: 4c58639 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.81 %
  • code
  • 91.11 %
  • assert
  • 97.75 %
  • func
  • 65.58 %
  • block
  • 91.08 %
  • line
  • 93.43 %
  • branch
  • 83.65 %
  • toggle
  • 97.99 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
89.47%
V2S
88.89%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 79.722us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 67.455us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 64.289us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 58.894us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 594.296us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 111.122us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 83.440us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 58.894us 1 1 100.00
aes_csr_aliasing 3.000s 111.122us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 67.455us 1 1 100.00
aes_config_error 2.000s 143.472us 1 1 100.00
aes_stress 2.000s 69.457us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 67.455us 1 1 100.00
aes_config_error 2.000s 143.472us 1 1 100.00
aes_stress 2.000s 69.457us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 69.457us 1 1 100.00
aes_b2b 4.000s 526.135us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 69.457us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 2.000s 67.455us 1 1 100.00
aes_config_error 2.000s 143.472us 1 1 100.00
aes_stress 2.000s 69.457us 1 1 100.00
aes_alert_reset 33.000s 10014.037us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 98.475us 1 1 100.00
aes_config_error 2.000s 143.472us 1 1 100.00
aes_alert_reset 33.000s 10014.037us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 143.304us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 117.608us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 4.000s 277.045us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 33.000s 10014.037us 0 1 0.00
stress 1 1 100.00
aes_stress 2.000s 69.457us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 69.457us 1 1 100.00
aes_sideload 3.000s 156.360us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 131.406us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 9.000s 10151.043us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 2.000s 67.993us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 118.204us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 222.057us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 222.057us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 64.289us 1 1 100.00
aes_csr_rw 2.000s 58.894us 1 1 100.00
aes_csr_aliasing 3.000s 111.122us 1 1 100.00
aes_same_csr_outstanding 2.000s 138.473us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 64.289us 1 1 100.00
aes_csr_rw 2.000s 58.894us 1 1 100.00
aes_csr_aliasing 3.000s 111.122us 1 1 100.00
aes_same_csr_outstanding 2.000s 138.473us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 153.608us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 16.000s 10009.200us 0 1 0.00
aes_control_fi 2.000s 61.710us 1 1 100.00
aes_cipher_fi 2.000s 58.180us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 247.099us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 247.099us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 247.099us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 247.099us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 328.026us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 2.000s 787.433us 1 1 100.00
aes_tl_intg_err 3.000s 281.211us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 281.211us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 33.000s 10014.037us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 247.099us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 247.099us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 2.000s 67.455us 1 1 100.00
aes_stress 2.000s 69.457us 1 1 100.00
aes_alert_reset 33.000s 10014.037us 0 1 0.00
aes_core_fi 2.000s 100.943us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 2.000s 67.993us 1 1 100.00
aes_config_error 2.000s 143.472us 1 1 100.00
aes_stress 2.000s 69.457us 1 1 100.00
aes_core_fi 2.000s 100.943us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 247.099us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 122.293us 1 1 100.00
aes_stress 2.000s 69.457us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 69.457us 1 1 100.00
aes_sideload 3.000s 156.360us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 122.293us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 122.293us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 122.293us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 122.293us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 122.293us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 69.457us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 69.457us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 16.000s 10009.200us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 16.000s 10009.200us 0 1 0.00
aes_control_fi 2.000s 61.710us 1 1 100.00
aes_cipher_fi 2.000s 58.180us 1 1 100.00
aes_ctr_fi 2.000s 49.302us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 16.000s 10009.200us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 16.000s 10009.200us 0 1 0.00
aes_control_fi 2.000s 61.710us 1 1 100.00
aes_cipher_fi 2.000s 58.180us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 58.180us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 16.000s 10009.200us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 16.000s 10009.200us 0 1 0.00
aes_control_fi 2.000s 61.710us 1 1 100.00
aes_ctr_fi 2.000s 49.302us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 16.000s 10009.200us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 16.000s 10009.200us 0 1 0.00
aes_control_fi 2.000s 61.710us 1 1 100.00
aes_cipher_fi 2.000s 58.180us 1 1 100.00
aes_ctr_fi 2.000s 49.302us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 33.000s 10014.037us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 16.000s 10009.200us 0 1 0.00
aes_control_fi 2.000s 61.710us 1 1 100.00
aes_cipher_fi 2.000s 58.180us 1 1 100.00
aes_ctr_fi 2.000s 49.302us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 16.000s 10009.200us 0 1 0.00
aes_control_fi 2.000s 61.710us 1 1 100.00
aes_cipher_fi 2.000s 58.180us 1 1 100.00
aes_ctr_fi 2.000s 49.302us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 16.000s 10009.200us 0 1 0.00
aes_control_fi 2.000s 61.710us 1 1 100.00
aes_ctr_fi 2.000s 49.302us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 16.000s 10009.200us 0 1 0.00
aes_ghash_fi 1.000s 53.300us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 16.000s 10009.200us 0 1 0.00
aes_control_fi 2.000s 61.710us 1 1 100.00
aes_cipher_fi 2.000s 58.180us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
aes_stress_all_with_rand_reset 15.000s 555.099us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred!
aes_alert_reset 112939466300045257487585962481024509464022317323697179048733846268218060745475 1121
UVM_INFO @ 10014036523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 93003663771732740296763337263766753637358145580024063299702264742293589003043 1211
UVM_INFO @ 10151043077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred!
aes_fi 59647810447708903928508786034385797888046663163651769954659362635855474599518 584
UVM_INFO @ 10009200093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---