Simulation Results: clkmgr

 
27/04/2026 19:39:13 DVSim: v1.32.0 sha: 4c58639 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 76.44 %
  • code
  • 69.55 %
  • assert
  • 88.22 %
  • func
  • 71.54 %
  • line
  • 82.21 %
  • branch
  • 87.42 %
  • cond
  • 78.50 %
  • toggle
  • 99.62 %
  • FSM
  • 0.00 %
Validation stages
V1
83.33%
V2
69.23%
V2S
50.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.000s 29.530us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.830s 25.285us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.770s 23.786us 1 1 100.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 0.580s 2.198us 0 1 0.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.100s 34.698us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.370s 35.342us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.770s 23.786us 1 1 100.00
clkmgr_csr_aliasing 1.100s 34.698us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.840s 19.954us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.330s 45.111us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.700s 13.118us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.000s 29.530us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.810s 7.990us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.650s 4.312us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.810s 7.990us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.720s 2.236us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.910s 24.256us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.470s 59.206us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.470s 59.206us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
clkmgr_csr_hw_reset 0.830s 25.285us 1 1 100.00
clkmgr_csr_rw 0.770s 23.786us 1 1 100.00
clkmgr_csr_aliasing 1.100s 34.698us 1 1 100.00
clkmgr_same_csr_outstanding 0.960s 33.159us 0 1 0.00
tl_d_partial_access 3 4 75.00
clkmgr_csr_hw_reset 0.830s 25.285us 1 1 100.00
clkmgr_csr_rw 0.770s 23.786us 1 1 100.00
clkmgr_csr_aliasing 1.100s 34.698us 1 1 100.00
clkmgr_same_csr_outstanding 0.960s 33.159us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 3.500s 300.527us 1 1 100.00
clkmgr_tl_intg_err 0.640s 4.085us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.730s 128.899us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.730s 128.899us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.730s 128.899us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.730s 128.899us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.730s 8.335us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.640s 4.085us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.810s 7.990us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.650s 4.312us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.730s 128.899us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.900s 30.993us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.770s 23.786us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 3.500s 300.527us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.770s 23.786us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.770s 23.786us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 3.500s 300.527us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.780s 16.125us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.430s 47.083us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b*
clkmgr_frequency 93078134480783856266225109713784822732061413191270876248261198376127814097829 78
UVM_INFO @ 7990443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b*
clkmgr_frequency_timeout 61120380325837327036904994471922391421040230608015702090164556654747833849392 78
UVM_INFO @ 4312207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 90445367405698979305738347015994153317522815566068753059038341689282633652614 161
UVM_INFO @ 47082761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 14600641663340121451402359772762758255155425184714868695191654828300229126329 77
UVM_INFO @ 2236149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed
clkmgr_regwen 101311092405211433056758577635554812801876885368144588098878271324401787882053 74
UVM_INFO @ 16124741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: *
clkmgr_shadow_reg_errors_with_csr_rw 40270465182082284365898678295467550330668067332344975801710823942132749075636 75
UVM_INFO @ 8335092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 64860240193809362758238638067445695190917496745452003472839531513160508095304 75
UVM_INFO @ 4085258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: *
clkmgr_csr_bit_bash 76774476703090148959260491096835638663604901621234525536829605220992921925886 75
UVM_INFO @ 2198406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:649) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
clkmgr_same_csr_outstanding 13346564336722127962052008471394672339433453695821262216503364432621213553971 76
UVM_INFO @ 33158928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---