Simulation Results: csrng

 
27/04/2026 19:39:13 DVSim: v1.32.0 sha: 4c58639 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.21 %
  • code
  • 92.37 %
  • assert
  • 93.23 %
  • func
  • 79.02 %
  • block
  • 97.05 %
  • line
  • 97.80 %
  • branch
  • 92.59 %
  • toggle
  • 93.37 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 79.879us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 57.327us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 39.820us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 22.000s 1669.752us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 4.000s 169.112us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 26.560us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 39.820us 1 1 100.00
csrng_csr_aliasing 4.000s 169.112us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 4.000s 157.820us 1 1 100.00
alerts 1 1 100.00
csrng_alert 12.000s 899.764us 1 1 100.00
err 1 1 100.00
csrng_err 1.000s 25.944us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 2.000s 25.998us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 2.000s 25.998us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 223.000s 15318.224us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 15.465us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 39.326us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 2.000s 31.924us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 2.000s 31.924us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 57.327us 1 1 100.00
csrng_csr_rw 2.000s 39.820us 1 1 100.00
csrng_csr_aliasing 4.000s 169.112us 1 1 100.00
csrng_same_csr_outstanding 4.000s 150.936us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 57.327us 1 1 100.00
csrng_csr_rw 2.000s 39.820us 1 1 100.00
csrng_csr_aliasing 4.000s 169.112us 1 1 100.00
csrng_same_csr_outstanding 4.000s 150.936us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 4.000s 246.621us 1 1 100.00
csrng_tl_intg_err 5.000s 142.765us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 3.000s 38.910us 1 1 100.00
csrng_csr_rw 2.000s 39.820us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 12.000s 899.764us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 223.000s 15318.224us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 4.000s 157.820us 1 1 100.00
csrng_err 1.000s 25.944us 1 1 100.00
csrng_sec_cm 4.000s 246.621us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 4.000s 157.820us 1 1 100.00
csrng_err 1.000s 25.944us 1 1 100.00
csrng_sec_cm 4.000s 246.621us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 4.000s 157.820us 1 1 100.00
csrng_err 1.000s 25.944us 1 1 100.00
csrng_sec_cm 4.000s 246.621us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 4.000s 157.820us 1 1 100.00
csrng_err 1.000s 25.944us 1 1 100.00
csrng_sec_cm 4.000s 246.621us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 4.000s 157.820us 1 1 100.00
csrng_err 1.000s 25.944us 1 1 100.00
csrng_sec_cm 4.000s 246.621us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 12.000s 899.764us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 4.000s 157.820us 1 1 100.00
csrng_err 1.000s 25.944us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 223.000s 15318.224us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 12.000s 899.764us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 5.000s 142.765us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 4.000s 157.820us 1 1 100.00
csrng_err 1.000s 25.944us 1 1 100.00
csrng_sec_cm 4.000s 246.621us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 4.000s 157.820us 1 1 100.00
csrng_err 1.000s 25.944us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 4.000s 157.820us 1 1 100.00
csrng_err 1.000s 25.944us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 4.000s 157.820us 1 1 100.00
csrng_err 1.000s 25.944us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 4.000s 157.820us 1 1 100.00
csrng_err 1.000s 25.944us 1 1 100.00
csrng_sec_cm 4.000s 246.621us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 4.000s 157.820us 1 1 100.00
csrng_err 1.000s 25.944us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 0.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*])
csrng_cmds 102394775494750576492625630652878385533359652454360087640665803652383865790380 130
UVM_INFO @ 25997955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed!
csrng_stress_all_with_rand_reset 66910167238252130478714592875229043489596444495141746865452216746023937930807 None