Simulation Results: dma

 
27/04/2026 19:39:13 DVSim: v1.32.0 sha: 4c58639 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.11 %
  • code
  • 92.17 %
  • assert
  • 95.97 %
  • func
  • 61.20 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 4.000s 280.287us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 8.000s 4350.081us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 4.000s 268.607us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 158.029us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 16.038us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 5.000s 598.354us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 7.000s 900.860us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 1.000s 28.040us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 16.038us 1 1 100.00
dma_csr_aliasing 7.000s 900.860us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 56.000s 22494.249us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 207.000s 20786.986us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 121.000s 24811.749us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 121.000s 24811.749us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 207.000s 20786.986us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 512.000s 174609.589us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 121.000s 24811.749us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 7.000s 2903.666us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 272.000s 105670.147us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 23.363us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 2.000s 16.407us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 63.693us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 63.693us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 158.029us 1 1 100.00
dma_csr_rw 1.000s 16.038us 1 1 100.00
dma_csr_aliasing 7.000s 900.860us 1 1 100.00
dma_same_csr_outstanding 2.000s 271.846us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 158.029us 1 1 100.00
dma_csr_rw 1.000s 16.038us 1 1 100.00
dma_csr_aliasing 7.000s 900.860us 1 1 100.00
dma_same_csr_outstanding 2.000s 271.846us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 14.000s 302.127us 1 1 100.00
dma_generic_stress 512.000s 174609.589us 1 1 100.00
dma_handshake_stress 121.000s 24811.749us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 5.000s 675.796us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 2.000s 97.683us 1 1 100.00
dma_sec_cm 2.000s 13.537us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 38.000s 13949.098us 1 1 100.00
dma_longer_transfer 5.000s 813.684us 1 1 100.00
dma_stress_all_with_rand_reset 7.000s 636.821us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 109741287009647311452478682389598575659737373374477258496876458191832597383095 127
UVM_INFO @ 636820610ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---